DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 1-14 and 16-21 are pending in the Amendment filed 01/23/2026.
The prior art rejections of record are withdrawn in view of Applicant’s amendments independent claims 1, 12, and 18 (requiring “an exposed surface area of the first metal layer to a surface area of the wafer where the dielectric structure is disposed is greater than approximately 5%.”).
However, claims 1-14 and 16-21 are rejected in view of newly cited reference to Adusumilli et al. (US 20180082845 A1), as set forth below.
Additionally, claims 1-14 and 16-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Response to Arguments
Applicant's arguments, see “Remarks” filed 01/23/2026, have been fully considered but they are not persuasive.
Applicant’s arguments, see “Remarks” filed 01/23/2026, with respect to claims 1, 12, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly cited reference to Adusumilli et al. (US 20180082845 A1) teaches forming multiple interconnect structures in a series as part of a middle-of-line architecture providing metal contacts for logic circuitry components [Abstract; para. 0004], each comprising a barrier layer and copper fill, and formed within a dielectric layer [Abstract, Figs. 1-3; claim 1, para. 0040].
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-14 and 16-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claims 1, 12, and 18, the limitation “an exposed surface area of the first metal layer to a surface area of the wafer where the dielectric structure is disposed is greater than approximately 5%” renders the claim unclear, and therefore indefinite, because the claim does not clearly set forth what quantity exceeds 5% (i.e., 5% of what), or if the limitation intends to calculate a ratio. It appears the claim intends to compare surface areas, and would be made clear by stating simply “the exposed surface area of the first metal layer is greater than approximately 5% of the surface area of the wafer where the dielectric is disposed”.
Claims 2-11 are rejected as being dependent upon rejected base claim 1.
Claims 13-14 and 16-17 are rejected as being dependent upon rejected base claim 12.
Claims 19-21 are rejected as being dependent upon rejected base claim 18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 12-13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ryan et al. (US 20150126028 A1), in view of Avenzino et al. (US 6121150 A), and Adusumilli et al. (US 20180082845 A1).
As to claim 1, Ryan discloses a method for chemical-mechanical polishing (CMP) [Abstract, para. 0008; Fig. 4-7], comprising:
forming a first metal layer 104 [para. 0007, “ruthenium”] and a second metal layer 105 [para. 0007, “copper interconnect 105”] in a dielectric structure 101 disposed over a wafer [Fig. 4; Abstract], wherein the second metal layer 105 is formed over a portion of the first metal layer 104 [Fig. 4, para. 0024];
removing a portion of the second metal layer 105 to expose the first metal layer 104 [Fig. 1-2],
providing a first composition to remove a portion of the first metal layer 104 [para. 0030, para. 0032; But see also: para. 0008, para. 0024; Fig. 1-2, Fig. 4];
providing a second composition to form a protecting layer 125 over the second metal layer 105 [para. 0025-26, para. 0030, para. 0032];
removing the protecting layer 125 to expose the second metal layer 105 [para. 0032-33].
Ryan [para. 0032, Fig. 7] fails to explicitly disclose:
performing a chemical mechanical polishing (CMP) operation to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure, wherein a top surface of the first metal layer, a top surface of the second metal layer and a top surface of the dielectric structure form a flush surface.
However, Ryan discloses that conventional steps to form an integrated circuit may be performed after the etching step of removing the protective layer [para. 0033], and further that forming an interconnect structure, as described by Ryan at para. 0004, is one such conventional step.
Moreover, Avenzino et al. (US 6121150 A) discloses a conventional method of forming an interconnect [Figs. 3A-3E], comprising:
performing a chemical mechanical polishing (CMP) operation to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure, wherein a top surface of the first metal layer, a top surface of the second metal layer and a top surface of the dielectric structure form a flush surface [col. 11, lines 1-13].
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the step of performing additional steps, of Ryan, to include forming an interconnect structure, including performing a CMP step to form a flush surface among the barrier, conductive, and dielectric layers, of Avenzino because it is a conventional step in forming an interconnect structure, as taught by Avenzino [Figs. 3A-3E; col. 11, lines 1-13].
Furthermore, a rationale to support a conclusion that a claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. See MPEP §§ 2143 and 2143.02.
Here, Ryan discusses a problem in the prior art arises when performing a CMP process to form an interconnect structure that results in dishing in the final structure [para. 0008-0010]. The solution presented by Ryan produces an intermediate structure [Fig. 7] which would reduce the occurrence of dishing within the conventional CMP step of Avenzino to form a final interconnect structure. That is, each of claimed elements could have been combined by known methods with no change in their respective functions, and would have yielded nothing more than predictable results.
As to amended claim 1, Ryan discloses removing a portion of the second metal layer to expose the first metal layer [Figs. 1-2], but fails to explicitly disclose:
wherein an exposed surface area of the first metal layer to a surface area of the wafer where the dielectric structure is disposed is greater than approximately 5% after the removal of the portion of the second metal layer.
However, Adusumilli et al. (US 20180082845 A1) teaches forming multiple interconnect structures in a series as part of a middle-of-line architecture providing metal contacts for logic circuitry components [Abstract; para. 0004], each comprising a barrier layer and copper fill, and formed within a dielectric layer [Abstract, Figs. 1-3; claim 1, para. 0040].
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a single interconnect structure, of Ryan, to include forming multiple interconnect structures as part of a middle-of-line architecture, of Adusumilli, in order to form multiple metal contacts for logic circuitry components in a semiconductor device, as taught by Adusumilli [Abstract, para. 0004, Figs. 1-3].
As to claim 2, modified Ryan discloses the method of claim 1, wherein the first metal layer and the second metal layer comprise different metals [para. 0007].
As to claim 3, modified Ryan discloses the method of claim 1, wherein the first metal layer comprises noble metals [para. 0007, “ruthenium”].
As to claim 4, modified Ryan discloses the method of claim 1, wherein a thickness of the second metal layer 105 is greater than a thickness of the first metal layer 104 [para. 0007, Fig. 4].
As to claim 6, modified Ryan discloses the method of claim 1, wherein the first composition includes perbromic acid (HBrO₄) or perbromate, perchloric acid (HCIO₄) or perchlorate, or chlorite and chlorate, bromite and bromate [Ryan, para. 0039, “NaHClO”].
As to claim 12, modified Ryan discloses a method for chemical-mechanical polishing (CMP) [Abstract, para. 0008; Fig. 4-7], comprising:
forming a noble metal layer 104 and a copper feature 105 over noble metal layer 104 in a dielectric structure 101 [para. 0004, para. 0007-0008; Fig. 1-2, Fig. 4];
forming a protecting layer 125 over the copper feature 105 [Fig. 5; para. 0025, para. 0026 “protective layer”];
etching a portion of the noble metal layer after the forming of the protecting layer [Fig. 6, para. 0032];
removing the protecting layer from the copper feature [para. 0032].
Ryan [para. 0032, Fig. 7] fails to explicitly disclose:
performing a chemical mechanical polishing (CMP) operation to remove a portion of the noble metal layer, a portion of the copper feature and a portion of the dielectric structure, wherein a top surface of the noble metal layer, a top surface of the copper feature and a top surface of the dielectric structure form a flush surface.
However, Ryan discloses that conventional steps to form an integrated circuit may be performed after the etching step of removing the protective layer [para. 0033], and further that forming an interconnect structure, as described by Ryan at para. 0004, is one such conventional step.
Moreover, Avenzino et al. (US 6121150 A) discloses a conventional method of forming an interconnect [Figs. 3A-3E], comprising:
performing a chemical mechanical polishing (CMP) operation to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure, wherein a top surface of the first metal layer, a top surface of the second metal layer and a top surface of the dielectric structure form a flush surface [col. 10, line 54 – col. 11, line 13].
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the step of performing additional steps, of Ryan, to include forming an interconnect structure, including performing a CMP step to form a flush surface among the barrier, conductive, and dielectric layers, of Avenzino because it is a conventional step in forming an interconnect structure, as taught by Avenzino [Figs. 3A-3E; col. 11, lines 1-13].
Furthermore, a rationale to support a conclusion that a claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. See MPEP §§ 2143 and 2143.02.
Here, Ryan discusses a problem in the prior art arises when performing a CMP process to form an interconnect structure that results in dishing in the final structure [para. 0008-0010]. The solution presented by Ryan produces an intermediate structure [Fig. 7] which would reduce the occurrence of dishing within the conventional CMP step of Avenzino to form a final interconnect structure. That is, each of claimed elements could have been combined by known methods with no change in their respective functions, and would have yielded nothing more than predictable results.
As to amended claim 12, Ryan discloses removing a portion of the second metal layer to expose the first metal layer [Figs. 1-2], but fails to explicitly disclose:
wherein an exposed surface area of the first metal layer to a surface area of the wafer where the dielectric structure is disposed is greater than approximately 5% after the removal of the portion of the second metal layer.
However, Adusumilli et al. (US 20180082845 A1) teaches forming multiple interconnect structures in a series as part of a middle-of-line architecture providing metal contacts for logic circuitry components [Abstract; para. 0004], each comprising a barrier layer and copper fill, and formed within a dielectric layer [Abstract, Figs. 1-3; claim 1, para. 0040].
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a single interconnect structure, of Ryan, to include forming multiple interconnect structures as part of a middle-of-line architecture, of Adusumilli, in order to form multiple metal contacts for logic circuitry components in a semiconductor device, as taught by Adusumilli [Abstract, para. 0004, Figs. 1-3].
As to claim 13, modified Ryan discloses the method of claim 12, wherein a top surface of the protecting layer 135 is higher than a topmost surface of the noble metal layer 104 after the etching of the portion of the noble metal layer [Fig. 6, para. 0032].
As to claim 16, modified Ryan discloses the method of claim 12, wherein the etching of the portion of the noble metal layer comprises applying a second composition, and the second composition comprises perbromic acid (HBrO₄) or perbromate, perchloric acid (HCIO₄) or perchlorate, or chlorite and chlorate, bromite and bromate [Ryan, para. 0039, “NaHClO”].
Claim 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Ryan et al. (US 20150126028 A1), in view of Avenzino et al. (US 6121150 A), Wijekoon et al. (US 20070099422 A1), and Adusumilli et al. (US 20180082845 A1).
As to claim 18, Ryan discloses a method for forming an interconnect structure, comprising:
forming a noble metal layer 104 in a dielectric structure 101 [para. 0004; Fig. 1-2, Fig. 4];
forming a seed layer over the noble metal layer [para. 0003];
forming a low resistivity conductive material layer 105 over the seed layer [para. 0004; Fig. 1-2, Fig. 4];
providing a first composition to remove a portion of the noble metal layer 104 [para. 0032, “wet etching process”];
providing a second composition to form a protecting layer over the low resistivity conductive material layer and the seed layer [Fig. 5; para. 0025, para. 0026 “protective layer”; para. 0030, “In the case of liquid thiol exposure the chemical could be used as part of the wet etch process”];
removing the protecting layer to expose the low resistivity conductive material layer and the seed layer [para. 0032].
Ryan fails to explicitly disclose:
forming a seed layer over the noble metal layer
removing a portion of the low resistivity conductive material layer, a portion of the seed layer, a portion of the noble metal layer, and a portion of the dielectric structure to form an interconnect structure in the dielectric structure,, wherein a top surface of the noble metal layer, a top surface of the seed layer, a top surface of the low conductive material layer and a top surface of the dielectric structure form a flush surface.
Ryan fails to explicitly disclose the above emphasized limitations [para. 0032, Fig. 7].
However, Ryan discloses that conventional steps to form an integrated circuit may be performed after the etching step of removing the protective layer [para. 0033], and further that forming an interconnect structure, as described by Ryan at para. 0004, is one such conventional step.
Moreover, Avenzino et al. (US 6121150 A) discloses a conventional method of forming an interconnect [Figs. 3A-3E], comprising:
forming a seed layer over the noble metal layer [col. 7, lines 17-24];
performing a chemical mechanical polishing (CMP) operation to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure, wherein a top surface of the first metal layer, a top surface of the second metal layer and a top surface of the dielectric structure form a flush surface [col. 10, line 54 – col. 11, line 13].
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the step of performing additional steps, of Ryan, to include forming an interconnect structure, including forming a seed layer, and performing a CMP step to form a flush surface among the barrier, conductive, seed, and dielectric layers, of Avenzino because it is a conventional step in forming an interconnect structure, as taught by Avenzino [Figs. 3A-3E; col. 11, lines 1-13], and as to the seed layer, because it is conventional known to improve adhesion of the copper layer to the barrier layer, as taught by Avenzino [col. 7, lines 17-24].
Furthermore, a rationale to support a conclusion that a claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. See MPEP §§ 2143 and 2143.02.
Here, Ryan discusses a problem in the prior art arises when performing a CMP process to form an interconnect structure that results in dishing in the final structure [para. 0008-0010]. The solution presented by Ryan produces an intermediate structure [Fig. 7] which would reduce the occurrence of dishing within the conventional CMP step of Avenzino to form a final interconnect structure. That is, each of claimed elements could have been combined by known methods with no change in their respective functions, and would have yielded nothing more than predictable results.
Further as to the seed layer, Ryan fails to explicitly disclose an example comprising a seed layer, and indeed teaches that “[t]he electrical conductivity of ruthenium allows for direct plating of copper onto the ruthenium, which obviates the need for a copper seed layer” [para. 0006].
However, Wijekoon teaches an electroless copper deposition method [Abstract], which provides a bulk copper layer free of voids or seams, and that leaves the substrate field free of copper material [para. 0009], comprising:
a) deposition of a barrier layer (e.g., ALD or PVD of tantalum nitride); b) deposition of ruthenium layer by ALD or PVD; c) expose substrate to annealing process; d) deposition of seed copper by electroless, ECP or PVD; and e) deposition of bulk copper by electroless or ECP. [para. 0054].
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of electroplating the bulk copper layer to ruthenium liner, of modified Ryan, to include forming a copper seed layer on the ruthenium layer and forming the bulk copper layer through electroless deposition, of Wijekoon, in order to form a bulk copper layer free of voids or seams, and that leaves the substrate field free of copper material, as taught by Wijekoon [para. 0009].
As to amended claim 18, Ryan discloses removing a portion of the second metal layer to expose the first metal layer [Figs. 1-2], but fails to explicitly disclose:
wherein an exposed surface area of the first metal layer to a surface area of the wafer where the dielectric structure is disposed is greater than approximately 5% after the removal of the portion of the second metal layer.
However, Adusumilli et al. (US 20180082845 A1) teaches forming multiple interconnect structures in a series as part of a middle-of-line architecture providing metal contacts for logic circuitry components [Abstract; para. 0004], each comprising a barrier layer and copper fill, and formed within a dielectric layer [Abstract, Figs. 1-3; claim 1, para. 0040].
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a single interconnect structure, of Ryan, to include forming multiple interconnect structures as part of a middle-of-line architecture, of Adusumilli, in order to form multiple metal contacts for logic circuitry components in a semiconductor device, as taught by Adusumilli [Abstract, para. 0004, Figs. 1-3].
As to claim 19, modified Ryan discloses the method of Claim 18, wherein the first composition and the second composition is simultaneously provided [Ryan, para. 0030, “In the case of liquid thiol exposure the chemical could be used as part of the wet etch process”].
As to claim 20, modified Ryan discloses the method of Claim 18, further comprising forming a diffusion barrier layer 103 prior to the forming of the noble metal layer 104 [para. 0008].
As to claim 21, modified Ryan discloses the method of claim 18, wherein the first composition comprises perbromic acid (HBrO₄) or perbromate, perchloric acid (HCIO₄) or perchlorate, or chlorite and chlorate, bromite and bromate [Ryan, para. 0039, “NaHClO”].
Claims 5, 7-11, 14, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ryan et al. (US 20150126028 A1), in view of Avenzino et al. (US 6121150 A), and Adusumilli et al. (US 20180082845 A1), as applied to claims 1-4, 6, 12-13, and 16 above, and further in view of Lippy et al. (US 20200190673 A1).
As to claim 5, modified Ryan discloses the method of claim 1, but fails to explicitly disclose:
wherein an etching rate of the mixture on the first metal layer is greater than approximately 5 A/min.
However, Lippy discloses an etching composition for ruthenium exhibiting etching rates of ruthenium in excess of 20 Angstroms per minute [Abstract], comprising: periodate compounds, alkylammonium hydroxides, carbonate or bicarbonate buffers, and water [Abstract], and further comprising corrosion inhibitors including benzotriazole (BTA), triazole derivatives, thioazole derivatives, and tetrazole derivatives [para. 0026] in amounts effective to coat the metal surface and provide a barrier for the transport of oxygen or water to the metal surface [para. 0026].
[0020] In one embodiment, the composition comprises (as starting material ingredients) about 93.923% water, 3.494% tetramethylammonium hydroxide, 2.108% H5I06, 0.475% CO.sub.2, and possesses a pH of about ~10.8. In another embodiment, the composition is comprised of approximately 94 weight percent water, 3.5 weight percent tetramethylammonium hydroxide, and about 0.5 weight percent of the carbonate/bicarbonate buffering compound.[para. 0020]
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of wet etching ruthenium selectively over copper, of Ryan, to include applying the ruthenium selective wet etching composition, of Lippy, because it is an effective ruthenium etching composition, as taught by Lippy [Abstract].
As to claim 7, modified Ryan discloses the method of claim 1, wherein the first composition and the second composition are simultaneously provided to form a mixture [Lippy, para. 0020, para. 0026].
As to claim 8, modified Ryan discloses the method of claim 7, wherein a concentration of the first composition in the mixture is between approximately 100 ppm and approximately 20,000 ppm [Lippy, para. 0026, effective amount].
Here, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the composition of Lippy to include an amount of the corrosion inhibitor [para. 0026] between 100 and 20,000 ppm because Lippy teaches to use of the corrosion inhibitor to an effective amount for the purpose of coating the metal surface and provide a barrier for the transport of oxygen or water to the metal surface and one of ordinary skill in the art would know to use as much or as little as necessary to achieve the desired result and it is not inventive to discover the optimum or workable ranges by routine experimentation, see MPEP 2144.05.
As to claim 9, modified Ryan discloses the method of claim 7, wherein a concentration of the second composition in the mixture is between approximately 1 ppm and approximately 100,000 ppm [Lippy, para. 0020].
As to claim 10, modified Ryan discloses the discloses the method of claim 7, wherein a pH of the mixture is between approximately 5.0 and approximately 14.0 [Lippy, para. 0020, “~10.8”; Table 1].
As to claim 11, modified Ryan discloses the method of claim 7, wherein a temperature of the mixture is between approximately 0°C and approximately 80°C [Lippy, para. 0024, “a temperature in a range of from about 20°C. to about 90°C”].
As to claim 14, modified Ryan discloses the method of claim 12, but fails to explicitly disclose:
wherein the forming of the protecting layer comprises applying a first composition, and the first composition form covalent bonds and dipolar bonds with the copper layer [para. 0030].
However, Lippy discloses an etching composition for ruthenium exhibiting etching rates of ruthenium in excess of 20 Angstroms per minute [Abstract], comprising: periodate compounds, alkylammonium hydroxides, carbonate or bicarbonate buffers, and water [Abstract], and further comprising corrosion inhibitors including benzotriazole (BTA), triazole derivatives, thioazole derivatives, and tetrazole derivatives [para. 0026] in amounts effective to coat the metal surface and provide a barrier for the transport of oxygen or water to the metal surface [para. 0026].
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of wet etching ruthenium selectively over copper, in conjunction with forming a protective layer [para. 0030], of Ryan, to include applying the ruthenium selective wet etching composition, of Lippy, because it is an effective ruthenium etching composition, as taught by Lippy [Abstract].
As to claim 17, modified Ryan discloses the method of claim 16, wherein a process duration of the applying of the second composition is between approximately 15 seconds and approximately 10 minutes [Lippy, para. 0024, “about 1 minute to about 200 minutes”, which overlaps the claimed range and therefore supports a prima facie case of obviousness].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER M REMAVEGE whose telephone number is (571)270-5511. The examiner can normally be reached Monday-Friday 10:00 AM - 3:30 PM.
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/CHRISTOPHER REMAVEGE/Examiner, Art Unit 1713
/BINH X TRAN/Primary Examiner, Art Unit 1713
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