CTNF 18/648,641 CTNF 98866 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 07/10/2025 and 10/22/2025 are being considered by the examiner. Drawings The drawings submitted on 04/29/2024 are being considered by the examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-9, 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20230307370 A1) in view of Murakami (US 20180286673 A1) . Regarding claim 1 , Lee discloses a semiconductor device, comprising: a substrate (100); (Fig. 1) a conductive structure (115) disposed in the substrate (100) and protruding from the substrate, comprising: a conductive concave layer (140_2) disposed over the substrate (100) and comprising a top surface having a V-shaped cross-sectional profile; (Fig. 1) a top conductive layer (180_2) disposed over the conductive structure (115); (Fig. 1) Lee does not disclose: a conductive filling layer disposed on the conductive concave layer, wherein a surface of the conductive filling layer is concave with respect to the substrate; and a first barrier layer covering sidewalls of the conductive concave layer and the conductive filling layer, and covering a bottom surface of the conductive concave layer; and wherein the conductive filling layer comprises germanium or silicon germanium. However, Murakami discloses: a conductive filling layer (205) disposed on the conductive concave layer (204), wherein a surface of the conductive filling layer (205) is concave with respect to the substrate (201); ([0037], Fig. 2E) and a first barrier layer (203) covering sidewalls of the conductive concave layer (204) and the conductive filling layer (205), and covering a bottom surface of the conductive concave layer (204); ([0026], Fig. 2E) and wherein the conductive filling layer (205) comprises germanium (per [0037]) or silicon germanium. (Fig. 2E) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Lee and Murakami for a conductive filling layer disposed on the conductive concave layer, wherein a surface of the conductive filling layer is concave with respect to the substrate; and a first barrier layer covering sidewalls of the conductive concave layer and the conductive filling layer, and covering a bottom surface of the conductive concave layer; and wherein the conductive filling layer comprises germanium or silicon germanium in order to “a method of filling a recess in which as little of a void as possible is generated” (Murakami, [0006]) Regarding claim 2 , Murakami discloses the semiconductor device of claim 1, wherein the conductive concave layer (204) comprises silicon and/or germanium with substantially no oxygen and no nitrogen. ([0031, Fig. 2E) It would have been obvious to use the teachings of Murakami for reasons mentioned beforehand. Regarding claim 3 , Lee discloses the semiconductor device of claim 2, further comprising a first dielectric layer (110) disposed over the substrate (100), wherein the conductive structure (115) penetrates through the first dielectric layer (110). (Fig. 1) Regarding claim 4 , Lee discloses the semiconductor device of claim 3, further comprising an epitaxial layer (per [0024]) disposed between the substrate (100) and the first dielectric layer (110). (Fig. 1) Regarding claim 5 , Lee discloses the semiconductor device of claim 4, further comprising a second barrier layer (180_1) disposed between the conductive structure (115) and the top conductive layer (180_2). ([0048], Fig. 1) Regarding claim 6 , Lee discloses the semiconductor device of claim 5, wherein the first dielectric layer (110) comprises a dielectric material comprising oxygen atoms and/or nitrogen atoms. ([0026, Fig. 1) Regarding claim 7 , Lee discloses the semiconductor device of claim 6, wherein the second barrier layer (180_1) comprises titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. ([0048], Fig. 1) Regarding claim 8 , Lee discloses the semiconductor device of claim 7, wherein the top conductive layer (180_2) comprises aluminum, tungsten, copper, or a combination thereof.([0049, Fig. 1) Regrading claim 9 , Lee discloses the semiconductor device of claim 8. Lee does not disclose wherein a width of the conductive concave layer and a width of the conductive filling layer are substantially equal. However, Murakami discloses: wherein a width of the conductive concave layer (204) and a width of the conductive filling layer (205) are substantially equal. (Fig. 2E) It would have been obvious to one skilled in the art before the effective filing date to combine the Lee and Murakami for a width of the conductive concave layer and a width of the conductive filling layer are substantially equal in order to “a method of filling a recess in which as little of a void as possible is generated” (Murakami, [0006]) Regarding claim 12 , Lee discloses the semiconductor device of claim 1, wherein the first barrier layer (140_1) comprises titanium (Ti), titanium nitride (TiN), or a combination thereof. ([0043], Fig. 1) Regarding claim 13 , Lee discloses the semiconductor device of claim 12. Lee does not explicitly disclose wherein a thickness of the first barrier layer on sidewalls of the conductive concave layer and the conductive filling layer is less than a thickness of the first barrier layer under the bottom surface of the conductive concave layer. However, Murakami discloses: first barrier layer (203) on sidewalls of the conductive concave layer (204) and the conductive filling layer (205) and under the bottom surface of the conductive concave layer (204). (Fig. 2E) It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Murakami to have first barrier on sidewalls of the conductive concave layer and the conductive filling layer and under the bottom surface of the conductive concave layer in order to have a “reduction in wiring resistance”. (Murakami, [0003]) Murakami does not explicitly disclose different thicknesses however, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for a thickness of the first barrier layer on sidewalls of the conductive concave layer and the conductive filling layer is less than a thickness of the first barrier layer under the bottom surface of the conductive concave layer with routine experiment and optimization. In re Woodruff , 16 USPQ2d 1935, 1937 (Fed. Cir. 1990) . 07-22-aia AIA Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Murakami (US 20180286673 A1) as applied to claim 9 above, and further in view of Guler (US 20220393007 A1) . Regarding claim 10 , Murakami discloses the semiconductor device of claim 9. Murakami does not disclose wherein a top surface of the conductive filling layer and a top surface of the first dielectric layer are substantially coplanar. However, Guler discloses: wherein a top surface of the conductive filling layer (212) and a top surface of the first dielectric layer (214) are substantially coplanar. ([0044], Fig. 2) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Murakami and Guler for wherein a top surface of the conductive filling layer and a top surface of the first dielectric layer are substantially coplanar so that “ space and layout constraints are somewhat relaxed”. (Guler, [0047]) 07-22-aia AIA Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Guler (US 20220393007 A1) as applied to claim 10 above, and further in view of Noh et al. (US 20230026976 A1) . Regarding claim 11 , Guler discloses the semiconductor device of claim 10. Guler does not disclose wherein the conductive filling layer and the conductive concave layer are separated from the first dielectric layer, the epitaxial layer and the substrate by the first barrier layer. However, Noh discloses: wherein the conductive filling layer (142b) and the conductive concave layer (372) are separated from the first dielectric layer (102), the epitaxial layer (per [0022]) and the substrate (100) by the first barrier layer (371). ([0087], Fig. 13) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Guler and Noh for the conductive filling layer and the conductive concave layer are separated from the first dielectric layer, the epitaxial layer and the substrate by the first barrier layer so that “the resistance between a via and an upper wiring pattern may be reduced” (Guler, [0112]) 07-22-aia AIA Claim s 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Murakami (US 20180286673 A1) as applied to claim 13 above, and further in view of Gosset et al. (KR 20090057089 A) . Regarding claim 14 , Murakami discloses a first barrier layer (203) in the semiconductor device of claim 13. Murakami does not disclose wherein the first barrier layer is formed by an anisotropic deposition process. However, Gosset discloses: wherein the first barrier layer (122, “Referring to FIG. 2, the cover layer 122 is formed on top of the structure of FIG. 1 by way of non-selective and non-conformal deposition techniques such as, for example, non-selective and anisotropic chemical vapor deposition (CVD) techniques. Is deposited. The cover layer 122 is made of a dielectric material”) is formed by an anisotropic deposition process.(“ In one embodiment, showing selective anisotropic deposition of the cover layer during manufacture, the cover layer segment is disposed on the dielectric liner.”) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Murakami and Gosset for the first barrier layer is formed by an anisotropic deposition process in order to have “a stronger cover layer material”. (Gosset) Regarding claim 15 , Gosset discloses the semiconductor device of claim 14, further comprising a second dielectric layer (110) disposed on the first dielectric layer (105) and covering the top conductive layer (140). (Fig. 2-6) It would have been obvious to one skilled in the art before the effective filing date to use the teachings of Gosset for similar reasons mentioned beforehand. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897 Application/Control Number: 18/648,641 Page 2 Art Unit: 2897 Application/Control Number: 18/648,641 Page 3 Art Unit: 2897 Application/Control Number: 18/648,641 Page 4 Art Unit: 2897 Application/Control Number: 18/648,641 Page 5 Art Unit: 2897 Application/Control Number: 18/648,641 Page 6 Art Unit: 2897 Application/Control Number: 18/648,641 Page 7 Art Unit: 2897 Application/Control Number: 18/648,641 Page 8 Art Unit: 2897
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