DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 4-10, filed 07/11/2026, with respect to the rejection(s) of claim(s) 1-15 under U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Dewey et al. (US 20220102521 A1) in view of Hsu et al. (US 20200135647 A1).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Dewey et al. (US 20220102521 A1) in view of Hsu et al. (US 20200135647 A1).
Regarding claim 1, Dewey discloses a semiconductor device, comprising:
a substrate (142);
a conductive structure (154) disposed in the substrate and protruding from the substrate, comprising:
a conductive concave layer (158A) disposed over the substrate and comprising a top surface having a V-shaped cross-sectional profile;
a conductive filling layer (158B/C) disposed on the conductive concave layer, wherein a surface of the conductive filling layer is concave with respect to the substrate; and
a first barrier layer (158D) covering sidewalls of the conductive concave layer and the conductive filling layer, and covering a bottom surface of the conductive concave layer; and
wherein a top surface of the conductive filling layer (158B/C) and a top surface of the first barrier layer (158D) are coplanar; ([0036], Fig. 1C)
Dewey does not disclose:
a top conductive layer disposed over the conductive structure;
wherein the conductive filling layer comprises germanium or silicon germanium.
However, Hsu discloses:
a top conductive layer (66) disposed over the conductive structure (28, 30, 50); (Fig. 8)
wherein the conductive filling layer (50) comprises germanium or silicon germanium. ([0025])
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Dewey and Hsu to have a top conductive layer disposed over the conductive structure and wherein the conductive filling layer comprises germanium or silicon germanium in order to “improve the current fabrication” (HSU, [0004]) and performance of the device.
Regarding claim 2, Dewey discloses the semiconductor device of claim 1. Dewey does not disclose wherein the conductive concave layer comprises silicon and/or germanium with substantially no oxygen and no nitrogen.
However, Hsu discloses:
the conductive concave layer (50) comprises silicon and/or germanium (per [0025]) with substantially no oxygen and no nitrogen.
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Dewey and Hsu for the conductive concave layer comprises silicon and/or germanium with substantially no oxygen and no nitrogen in order to “improve the current fabrication” (Hsu, [0004]) and performance of the device.
Regarding claim 3, Hsu discloses the semiconductor device of claim 2, further comprising a first dielectric layer (46) disposed over the substrate (12), wherein the conductive structure (28, 30, 50) penetrates through the first dielectric layer (46). (Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings Hsu for similar reasons mentioned beforehand.
Regarding claim 4, Hsu discloses the semiconductor device of claim 3. Hsu does not disclose further comprising an epitaxial layer disposed between the substrate and the first dielectric layer.
However, Dewey discloses:
an epitaxial layer (144) disposed between the substrate (142) and the first dielectric layer (150). ([0036], Fig. 1C)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hsu and Dewey to have an epitaxial layer disposed between the substrate and the first dielectric layer in order to have “low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts.” (Dewey, [0108])
Claims 5-13 are rejected under 35 U.S.C. 103 as being unpatentable over Dewey et al. (US 20220102521 A1) as applied to claim 4, and further in view of Tang et al. (US 20230395719 A1)
Regarding claim 5, Dewey discloses the semiconductor device of claim 4. Dewey does not disclose further comprising a second barrier layer disposed between the conductive structure and the top conductive layer, wherein the second barrier layer covers the top surface of the conductive filling layer and the top surface of the first barrier layer.
However, Tang discloses:
a second barrier layer (60) disposed between the conductive structure (30) and the top conductive layer (58), wherein the second barrier layer (60) covers the top surface of the conductive filling layer (42) and the top surface of the first barrier layer (32). (Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Dewey and Tang to have a second barrier layer disposed between the conductive structure and the top conductive layer, wherein the second barrier layer covers the top surface of the conductive filling layer and the top surface of the first barrier layer in order to “improve the current fabrication” (Tang, [0004]) and performance of the device.
Regarding claim 6, Tang discloses the semiconductor device of claim 5. Tang does not disclose wherein the first dielectric layer comprises a dielectric material comprising oxygen atoms and/or nitrogen atoms.
However, Dewey discloses:
the first dielectric layer (158D) comprises a dielectric material comprising oxygen atoms and/or nitrogen atoms. ([0036], Fig. 1C)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Tang and Dewey for the first dielectric layer comprises a dielectric material comprising oxygen atoms and/or nitrogen atoms in order to have “low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts.” (Dewey, [0108])
Regarding claim 7, Dewey discloses the semiconductor device of claim 6. Dewey does not disclose wherein the second barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof.
However, Hsu discloses:
the second barrier layer (64) comprises titanium, titanium nitride, (per [0028]) tantalum, tantalum nitride, or a combination thereof.
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Dewey and Hsu for the second barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof in order to “improve the current fabrication” (HSU, [0004]) and performance of the device.
Regarding claim 8, Hsu discloses the semiconductor device of claim 7, wherein the top conductive layer (66) comprises aluminum, tungsten (per [0030]), copper, or a combination thereof.
It would have been obvious to use the teachings of Hsu for similar reasons mentioned beforehand.
Regarding claim 9, Hsu discloses the semiconductor device of claim 8. Hsu does not disclose wherein a width of the conductive concave layer and a width of the conductive filling layer are substantially equal.
However, Dewey discloses:
a width of the conductive concave layer (158A) and a width of the conductive filling layer (158B/C) are substantially equal. (Fig. 1C)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hsu and Dewey for a width of the conductive concave layer and a width of the conductive filling layer are substantially equal in order to have “low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts.” (Dewey, [0108])
Regarding claim 10, Dewey Fig. 1C discloses the semiconductor device of claim 9. Dewey Fig. 1C does not show wherein a top surface of the conductive filling layer and a top surface of the first dielectric layer are substantially coplanar.
However, Dewey Fig. 4C shows:
a top surface of the conductive filling layer (438) and a top surface of the first dielectric layer (410 in Fig. 4A) are substantially coplanar. (Fig. 4C)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings Dewey for similar reasons mentioned beforehand.
Regarding claim 11, Dewey Fig. 4C discloses the semiconductor device of claim 10. Dewey Fig. 4C does not show:
wherein the conductive filling layer and the conductive concave layer are separated from the first dielectric layer, the epitaxial layer and the substrate by the first barrier layer
However, Dewey Fig. 1C shows:
wherein the conductive filling layer (158B/C) and the conductive concave layer (158A) are separated from the first dielectric layer (150), the epitaxial layer (144) and the substrate (142) by the first barrier layer (158D). ([0036], Fig. 1C)
It would have been obvious to one skilled in the art before the effective filing date to use the teachings Dewey for similar reasons mentioned beforehand.
Regarding claim 12, Dewey discloses the semiconductor device of claim 1, wherein the first barrier layer (158D) comprises titanium (Ti), titanium nitride (TiN), (per [0036]) or a combination thereof wherein a top surface of the conductive concave layer (158A) is below the top surface of the conductive filling layer (158 B/C). (Fig. 1C)
Regarding claim 13, Dewey discloses the semiconductor device of claim 12, a thickness of the first barrier layer (158D) on sidewalls of the conductive concave layer (158A) and the conductive filling layer (158B/C) is less than a thickness of the first barrier layer (158D) under the bottom surface of the conductive concave layer (158A). (Fig. 1C)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Dewey et al. (US 20220102521 A1) as applied to claim 13 above, and further in view of Chou (US 20220399454 A1).
Regarding claim 14, Dewey discloses the semiconductor device of claim 13. Dewey does not disclose wherein the first barrier layer is formed by an anisotropic deposition process.
However, Chou discloses:
the first barrier layer (173) is formed by an anisotropic deposition process. ([0057])
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Dewey and Chou for the first barrier layer is formed by an anisotropic deposition process in order to have “a conductive contact having a barrier layer with different thicknesses” so that “the device performance may be enhanced” (Chou, [0103])
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chou (US 20220399454 A1) as applied to claim 14 above, and further in view of Noh et al. (US 20230026976 A1).
Regarding claim 15, Chou discloses the semiconductor device of claim 14. Chou does not disclose further comprising a second dielectric layer disposed on the first dielectric layer and covering the top conductive layer.
However, Noh discloses:
a second dielectric layer (103) disposed on the first dielectric layer (102) and covering the top conductive layer (130). (Fig. 6)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chou and Noh to have a second dielectric layer disposed on the first dielectric layer and covering the top conductive layer so that “the resistance between a via and an upper wiring pattern may be reduced” (Noh, [0112])
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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