Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 17 August 2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “dielectric cap disposed within inner sidewalls of the dielectric liner and extending from a top surface of the dielectric liner to an upper surface of the dielectric liner that is co-planar with upper surfaces of the barrier layer structure and the pair of metal lines” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Clevenger et al. (US Pat. Pub. 2014/0131880) in view of Lo et al. (US Pat. Pub. 2021/0193566).
The applied reference (Lo et al.) has a common Applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claim 1, Clevenger teaches an integrated chip, comprising:
a semiconductor substrate [fig. 7e, 12];
a dielectric layer disposed over the semiconductor substrate [fig. 7e, 602];
a pair of metal lines disposed over an upper surface of the dielectric layer [fig. 7e, 608];
a barrier layer structure extending along nearest neighboring sidewalls of the pair of metal lines, wherein the barrier layer structure comprises a different material than the dielectric layer [fig. 7e, 19 along sidewalls of 608, 19 disclosed in fig 6b, but present in 7e as well, paragraph [0091] teaches Ta, TaN, Ti, TiN among others for barrier material, paragraph [0092] teaches Cu, W, Al as material of 608]; and
a cavity defined by surfaces of the barrier layer structure, and the dielectric layer [fig. 7e, cavity 28 defined by 602 and 19].
Clevenger fails to teach the use of a dielectric liner on inner sidewalls of the barrier structure. However, Lo teaches a semiconductor device with a cavity structure containing a dielectric liner between a pair of metal lines helping to define a cavity [fig. 1, cavity 112, liner 118 between metal lines 114].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Lo into the method of Clevenger by forming a dielectric liner between inner sidewalls of the barrier layer structure, the cavity being defined by surfaces of the dielectric liner, the barrier layer and the dielectric layer. The ordinary artisan would have been motivated to modify Clevenger in the manner set forth above for at least the purpose of creating a device with a reduced k-value of the dielectric structure [Lo, paragraph [0017]].
Regarding claim 2, Clevenger in view of Lo teaches the integrated chip of claim 1, wherein the barrier layer structure is separated from the dielectric layer by the cavity [Clevenger, fig. 7e, portions of the barrier surrounding 608 are separated from the dielectric layer 602 by the cavity 28].
Regarding claim 3, Clevenger in view of Lo discloses the integrated chip of claim 1, further comprising:
A glue layer structure disposed between the pair of metal lines and the dielectric layer wherein the cavity is further defined by the glue layer structure [Lo, fig. 1, glue layer 110 between 114 and 104].
Regarding claim 6, Clevenger in view of Lo teaches the integrated chip of claim 1, wherein the barrier layer structure extends from a top surface of the pair of metal lines to contact the dielectric layer [Clevenger, fig. 7e, 19 extends from the top of 608 to the dielectric layer 602].
Allowable Subject Matter
Claims 8-14 and 21-26 are allowed.
Claims 4, 5 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a second pair of barrier structures separated from the first pair of barrier layer structures by a pair of cavities, wherein the pair of cavities are along a top surface of the dielectric layer, a bottom surface of the first and second pair of barrier layer structures and sidewalls of the first and second pair of barrier layer structures.
Regarding claim 21, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a blocking layer disposed on at least a portion of the upper surface of the dielectric layer between the first and second metal lines and a cavity disposed laterally between inner sidewalls of the first and second barrier layer structures and extending over the blocking layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOHN M PARKER/Primary Examiner, Art Unit 2899
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