CTNF 18/648,917 CTNF 77458 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 4/29/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections 07-29-01 AIA Claim s 2 and 3 are objected to because of the following informalities: Claim 2 recites “vertical aligned” in line 2. The examiner suggests “ vertical vertically aligned”. Claim 3 recites “vertical aligned” in line 2. The examiner suggests “ vertical vertically aligned” . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s). 07-21-aia AIA Claim (s) 1 through 5 and 7 through 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0221493) in view of Zhai (US 2018/0204820) Regarding claim 1. Kim teaches: A structure comprising: a package (fig 14:1000a; [para 0074]) comprising: a first die (fig 14:200; [para 0051]); a second die (fig 14:100; [para 0038,0042]) underlying and joined to the first die (fig 10:200; [para 0051]) and comprising: a semiconductor substrate (fig 10:110; [para 0036]); a plurality of through-vias (fig 14:130; [para 0036,0037]) in the semiconductor substrate (fig 14:110; [para 0036,0037]); and a plurality of metal pillars (fig 14:142; [para 0041]) electrically coupled to the plurality of through-vias (fig 14:130; [para 0041]); and an interconnect structure underlying the package, wherein the interconnect structure comprises: a polymer layer underlying and contacting some of the plurality of metal pillars; and a plurality of redistribution lines comprising portions in the polymer layer to physically contact the plurality of metal pillar s. Kim does not teach an interconnect structure underlying the package Zhai teaches: an interconnect structure (fig 5c:110; [para 0048]) underlying the package (fig 5c:100; [para 0049]), wherein the interconnect structure (fig 5c:110; [para 0048]) comprises: a polymer layer (fig 5c:114; [para 0029]) underlying and contacting some of the plurality of metal pillars (fig 5c:135; [para 0048]); and a plurality of redistribution lines (fig 5c:112; [para 0029]) comprising portions in the polymer layer (fig 5c:114; [para 0029]) to physically contact the plurality of metal pillars (fig 5c:135; [para 0048]). PNG media_image1.png 534 878 media_image1.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a interconnect layer underlying the package in order to redistribute signal and power between the packaged die and the mounting substrate (paragraph 26). Regarding claim 2. Kim in view of Zhai teaches the structure of claim 1, further Kim teaches: a first encapsulant (fig 14:310; [para 0058]) encapsulating the first die (fig 14:200; [para 0051]) therein, wherein a first edge of the first encapsulant (fig 14:310; [para 0058]) is vertical aligned to a second edge of the second die (fig 14:100; [para 0035]). PNG media_image2.png 426 648 media_image2.png Greyscale Regarding claim 3. Kim in view of Zhai teaches the structure of claim 2, Kim teaches: the semiconductor substrate (fig 14:110; [para 0040]) of the second die (fig 14:100; [para 0040]) comprises a third edge vertical aligned to the first edge of the first encapsulant (fig 14:310; [para 0058]). PNG media_image3.png 437 654 media_image3.png Greyscale Regarding claim 4. Kim in view of Zhai teaches the structure of claim 2, Kim teaches: the second die (fig 14:100; [para 0068]) comprises a probe pad (fig 14:175; [para 0068]) at a top surface of the second die (fig 14:100; [para 0068]), wherein an entire top surface of the probe pad (fig 14:175; [para 0068]) contacts the first encapsulant (fig 14:310; [para 0058]) to form an interface. Regarding claim 5. Kim in view of Zhai teaches the structure of claim 4, Kim teaches: the probe pad (fig 14:175; [para 0046]) comprises copper (; [para 0046]). Regarding claim 7. Kim in view of Zhai teaches the structure of claim 2, Kim teaches: a second encapsulant (fig 14:340; [para 0127]) encapsulating the first die (fig 14:200; [para 0115]), the second die (fig 14:100; [para 0115]), and the first encapsulant (fig 14:310; [para 0127]) therein Regarding claim 8 Kim in view of Zhai teaches the structure of claim 7, Kim teaches: outer edges of the second encapsulant (fig 14:340; [para 0127]) and the interconnect structure (fig 14:2000; [para 0122]) are vertically aligned. Zhai teaches: outer edges of the second encapsulant (fig 5c:140; [para 0041]) and the interconnect structure (fig 5c:110; [para 0041]) are vertically aligned. Regarding claim 9. Kim in view of Zhai teaches the structure of claim 1, Kim teaches: a dielectric layer (fig 14:124[103]), wherein the plurality of metal pillars (fig 14:142; [para 0041]) are in the dielectric layer (fig 14:124[103]), and wherein edges of the dielectric layer (fig 14:124[103]) and the semiconductor substrate (fig 14:110; [para 0036,0037]) are vertically aligned (fig 14). Regarding claim 10. Kim in view of Zhai teaches the structure of claim 1, Kim teaches: Portions (fig 14:2000; [para 0122]) of the polymer layer and the plurality of redistribution lines are laterally beyond the package (fig 10,14:1000a; [para 0126]). Zhai teaches: portions of the polymer layer (fig 1,5c:114; [para 0029]) and the plurality of redistribution lines (fig 1,5c:112; [para 0029]) are laterally beyond the package (fig 5c:130; [para 0026]) . 07-21-aia AIA Claim (s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0221493) in view of Zhai (US 2018/0204820) as applied to claim 2 and further in view of Fu (US 2021/0066144) Regarding claim 6. Kim in view of Zhai teaches the structure of claim 2, above. Kim teaches: the second die (fig 14:100; [para 0068]) comprises: a probe pad (fig 14:175; [para 0068]) at a top surface of the second die (fig 14:100; [para 0068]); and a solder region over and contacting the probe pad (fig 14:175; [para 0068]), wherein an entire top surface of the solder region contacts the first encapsulant (fig 14:310; [para 0058]) to form an interface. Kim does not teach the region over the probe pad comprises solder. Fu teaches: a probe pad (fig 6:264; [para 0052]) at a top surface of the second die (fig 6:215; [para 0051]); and a solder region (fig 6:265; [para 0052]) over and contacting the probe pad (fig 6:264; [para 0052]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the probe pad with a top region comprising solder in order to reduce probe wear, damage to underlying passivation and surface cracking (paragraph 50) 07-21-aia AIA Claim (s) 11, 12, 13, 14, 15, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0221493) in view of Zhai (US 2018/0204820) Regarding claim 11. Kim teaches: A structure comprising: a package (fig 14:1000a; [para 0074]) comprising: a device die (fig 14:100; [para 0038,0042]) comprising: a semiconductor substrate (fig 14:110; [para 0036,0037]); a through-via (fig 14:130; [para 0036,0037]) in the semiconductor substrate (fig 14:110; [para 0036,0037]); a package component (fig 14,200; [para 0051]) over and joining to the device die (fig 14:100; [para 0038,0042]); a first molding compound (fig 14: 310; [para 0058]) molding the package component (fig 14,200; [para 0051]) therein; a dielectric layer (fig 14:124; [para 0041]) underlying the semiconductor substrate (fig 14:110; [para 0036,0037]), wherein edges of the dielectric layer (fig 14:124; [para 0041]) are flush with corresponding edges of the first molding (fig 14: 310; [para 0058]) compound and the device die (fig 14:100; [para 0038,0042]); and a metal pillar (fig 14:142; [para 0041]) underlying and electrically connecting to the through-via (fig 14:130; [para 0036,0037]), wherein the metal pillar (fig 14:142; [para 0041]) is in the dielectric layer (fig 14:124; [para 0041]); and a redistribution line underlying the metal pillar, wherein a via of the redistribution line physically contacts the metal pillar . Kim does not teach a redistribution layer. Zhai teaches: a redistribution line (fig 5d:112; [para 0029]) underlying the metal pillar (fig 5c:135; [para 0041]), wherein a via of the redistribution line (fig 5c:112; [para 0029]) physically contacts the metal pillar (fig 5c:135; [para 0041]). PNG media_image4.png 502 906 media_image4.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a interconnect layer underlying the package in order to redistribute signal and power between the packaged die and the mounting substrate (paragraph 26). Regarding claim 12. Kim in view of Zhai teaches the structure of claim 11, above. Kim teaches: the device die (fig 14:100; [para 0038,0042]) comprises: a plurality of bond pads (fig 14:170; [para 0043]) joined to the package component (fig 14,200; [para 0051]); and a probe pad (fig 14:175; [para 0046]) in contact with the first molding compound (fig 14:310; [para 0058]). Regarding claim 13. Kim in view of Zhai teaches the structure of claim 12, above. Kim teaches: first top surfaces of the plurality of bond pads (fig 14:170; [para 0043]) are coplanar with a second top surface of the probe pad (fig 14:175; [para 0046]), and wherein an entirety of the second top surface of the probe pad (fig 14:175; [para 0046]) contacts the first molding compound (fig 14:310; [para 0058]). Regarding claim 14. Kim in view of Zhai teaches the structure of claim 12, above. Kim teaches: a second molding compound (fig 14:340; [para 0127]) comprising: a first top surface coplanar with a second top surface of the package component (fig 14:200; [para 0051]); and a first bottom surface coplanar with a second bottom surface of the metal pillar . Zhai teaches: a second molding compound (fig 5c:140; [para 0048]) comprising: a first top surface coplanar with a second top surface of the package component (fig 5c:130; [para 0047]); and a first bottom surface coplanar with a second bottom surface of the metal pillar (fig 5c:135; [para 0048]). Regarding claim 15. Kim in view of Zhai teaches the structure of claim 14, above. Zhai teaches: a portion of the redistribution line (fig 5c:112; [para 0029]) is directly underlying a portion of the second molding compound (fig 5c:140; [para 0048]). Regarding claim 17. Kim in view of Zhai teaches the structure of claim 14, above. Kim teaches: the first molding compound (fig 14:310; [para 0058]) and the second molding compound (fig 14:340; [para 0058]) have a distinguishable interface (fig 14) . 07-21-aia AIA Claim (s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0221493) in view of Zhai (US 2018/0204820) as applied to claim 15 and further in view of Yu (US 10157864) Regarding claim 16. Kim in view of Zhai teaches the structure of claim 15, above. Kim in view of Zhai does not teach an additional dielectric layer. Yu teaches: an additional dielectric layer (fig 2I:26; [column 7 lines 25-35]), wherein the redistribution line (fig 2I:36; [column 7 lines 25-35]) comprises a part in the additional dielectric layer (fig 2I:26; [column 7 lines 25-35]), and wherein the additional dielectric layer (fig 2I:26; [column 7 lines 25-35]) comprises outer portions laterally beyond opposing edges of the package (fig 2l:25; [column 2 lines 30-40]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the structure to comprise additional dielectric layer in order to enable the fabrication of a multi-layer redistribution structure with metal lines embedded therein 07-21-aia AIA Claim (s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0221493) in view of Zhai (US 2018/0204820) Regarding claim 18. Kim teaches: A structure comprising: a first device die (fig 14:100; [para 0058]) comprising: a first plurality of electrical connectors (fig 14:240; [para 0054]); and a second plurality of electrical connectors (fig 14:175; [para 0046]), wherein the first plurality of electrical connectors (fig 14:240; [para 0054]) and the second plurality of electrical connectors (fig 14:175; [para 0046]) comprise: a first metal pillar (fig 14:170; [para 0054]); and a solder region (fig 14:244; [para 0053]) over the first metal pillar (fig 14:170; [para 0054]); second metal pillars (fig 14:142; [para 0041]) underlying the first plurality of electrical connectors (fig 14:240; [para 0054]) and the second plurality of electrical connectors (fig 14:175; [para 0046]) , wherein the second metal pillars (fig 14:142; [para 0041]) comprise vertical-and-straight edges (fig 14); a second device die (fig 14:200; [para 0058]) over and joined to the first device die (fig 14:100; [para 0058]) through the first plurality of electrical connectors (fig 14:240; [para 0054]); a molding compound (fig 14:310; [para 0058]) molding the second device die (fig 14:200; [para 0058]) and the second plurality of electrical connectors (fig 14:175; [para 0046]) therein, wherein the second plurality of electrical connectors (fig 14:175; [para 0046]) are overlapped by, and are in physical contact with, the molding compound (fig 14:310; [para 0058]); and an interconnect structure comprising: a polymer layer underlying and contacting some of the second metal pillars, wherein the polymer layer comprises portions laterally beyond opposing edges of the first device die; and a plurality of redistribution lines comprising portions in the polymer layer . Kim does not teach an interconnect structure. Zhai teaches: an interconnect structure (fig 5c:110; [para 0029]) comprising: a polymer layer (fig 5c:114; [para 0029]) underlying and contacting some of the second metal pillars (fig 5c:135; [para 0047]), wherein the polymer layer (fig 5c:114; [para 0029]) comprises portions laterally beyond opposing edges of the first device die (fig 5c:130; [para 0048]); and a plurality of redistribution lines (fig 5c:112; [para 0029]) comprising portions in the polymer layer (fig 5c:114; [para 0029]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a interconnect layer underlying the package in order to redistribute signal and power between the packaged die and the mounting substrate (paragraph 26). Regarding claim 19. Kim in view of Zhai teaches the structure of claim 18 Zhai teaches: an interconnect structure (fig 5c:110; [para 0029]) Kim teaches a second embodiment comprising: a package substrate (fig 15:3000; [para 0130,0131]) underlying and electrically coupling to the interconnect structure. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a package substrate in order to provide a mounting substrate for the package (paragraph 129) 07-21-aia AIA Claim (s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2013/0221493) in view of Zhai (US 2018/0204820) as applied to claim 18 and further in view of Fu (US 2021/0066144) Regarding claim 20. Kim in view of Zhai teaches the structure of claim 18, above Kim teaches: an entire top surface of the solder region is in contact with the molding compound (fig 14:310; [para 0058]). PNG media_image5.png 557 1013 media_image5.png Greyscale Kim in view of Zhai does not teach the top surface comprises a solder region Fu teaches: an entire top surface comprises the solder region (fig 6:265; [para 0052]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the second electrical connector with a top region comprising solder in order to reduce probe wear, damage to underlying passivation and surface cracking (paragraph 50) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.J.G/Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 Application/Control Number: 18/648,917 Page 2 Art Unit: 2817 Application/Control Number: 18/648,917 Page 4 Art Unit: 2817
Prosecution Insights