DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 01/09/2026 Amendment.
Claims 2-21 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,170,894 to Shaeffer et al. (hereafter Shaeffer).
Regarding independent claim 2, Shaeffer teaches a memory component (see FIG. 1), comprising:
a command/address (CA) interface (FIG. 1: connections for command bus 132 and address bus 134) configured to receive, from a controller (FIG. 1: DRAM controller 10), an inherent activate command (when DRAM is selected for any operation), a write command (FIG. 3: receiving write command in step 302), and associated address information (FIG. 3: receiving address in step 302);
a data interface configured to communicate, with the controller, data associated with the write command (FIG. 1: connections for DQ bus 136 for transmitting data);
CA parity error checking circuitry (FIG. 1: when CRC generator 150 generates CRC code for address separated from data, see 7:10-15) configured to:
determine, based on the activate command, the write command, and the associated address information, CA parity error information (see 4:4-23);
data cyclical redundancy check (CRC) error checking circuitry (FIG. 1: when CRC generator 150 generates CRC code for data separated from address, see 7:10-15) configured to:
determine, based on the data associated with the write command, data cyclical redundancy check (CRC) error information (see 4:4-23);
modulation circuitry configured to:
determine a modulated error information based on the CA parity error information and the data CRC error information associated with the data (FIG. 2B: e.g. modulating [An, Dn-k] or [An, Dn-k=1], see 6:66-7:9); and
a modulated error interface configured to transmit, to the controller, the modulated error information (FIG. 1: connections for EDC bus 138).
Regarding dependent claim 3, Shaeffer teaches wherein the associated address information includes a row address associated with the inherent activate command (see 3:34-43).
Regarding dependent claim 4, Shaeffer teaches wherein the associated address information includes a column address associated with the write command (see 3:34-43).
Regarding dependent claim 5, Shaeffer teaches wherein the associated address information includes a bank address associated with the write command (see 3:34-43).
Regarding dependent claim 6, Shaeffer teaches wherein the CA parity error information is based on the row address and the column address (i.e. address in general, see 3:34-43 and 6:66-7:9).
Regarding dependent claim 7, Shaeffer teaches wherein the modulated error information is based on an invertible function that uses the CA parity error information and the data CRC error information as inputs (see FIG. 2B).
Regarding dependent claim 8, Shaeffer implicitly teaches wherein the invertible function comprises an exclusive-OR of at least one bit of the CA parity error information and at least one bit of the data CRC error information (because CRC procedure implementing exclusive-ORs a fixed bit pattern into the polynomial division).
Regarding independent claim 9, Shaeffer teaches a memory component, comprising:
a command/address (CA) interface (FIG. 1: connections for command bus 132 and address bus 134) to receive, from a controller (FIG. 1: DRAM controller 10), an inherent activate command (when DRAM is selected for any operation), a write command (FIG. 3: receiving write command in step 302), and associated address information (FIG. 3: receiving address in step 302);
a data interface to receive, from the controller, data associated with the write command (FIG. 1: connections for DQ bus 136 for transmitting data);
CA parity calculation circuitry to, based on the activate command, the write command, and the associated address information, generate CA parity information (FIG. 1: when CRC generator 150 generates CRC code for address separated from data, see 7:10-15 and 4:4-23);
data cyclical redundancy check (CRC) calculation circuitry to, based on the data associated with the write command, generate CRC error checking information (FIG. 1: when CRC generator 150 generates CRC code for data separated from address, see 7:10-15 and see 4:4-23);
modulating function circuitry to, based on the CA parity information and the CRC error checking information, generate error indicating information (FIG. 2B: e.g. modulating [An, Dn-k] or [An, Dn-k=1], see 6:66-7:9); and
an error information interface to transmit, to the controller, the error indicating information (FIG. 1: connections for EDC bus 138).
Regarding dependent claim 10, Shaeffer teaches wherein the associated address information includes inherent activate command address information and write command address information (i.e. corresponding to row address and column address, see 3:34-43).
Regarding dependent claim 11, Shaeffer teaches wherein the activate command address information comprises a row address (see 3:34-43).
Regarding dependent claim 12, Shaeffer teaches wherein the write command address information comprises a column address (see 3:34-43).
Regarding dependent claim 13, Shaeffer teaches wherein the associated address information includes an activate command row address and a write command column address (i.e. corresponding to row address and column address, see 3:34-43).
Regarding dependent claim 14, Shaeffer teaches wherein the CA parity information is based on at least the activate command row address and the write command column address (i.e. corresponding to row address and column address, see 3:34-43).
Regarding dependent claim 15, Shaeffer teaches wherein the error indicating information is based on at least the activate command row address and the write command column address (i.e. corresponding to row address and column address, see 3:34-43).
Regarding dependent claim 16, Shaeffer teaches the error indicating information is based on an invertible function that is based on at least the activate command row address and the write command column address (i.e. corresponding to row address and column address, see 3:34-43).
Regarding independent claim 17, Shaeffer teaches a method of operating a memory component, comprising:
receiving, from a controller (FIG. 1: DRAM controller 10) and via a command/address (CA) interface (FIG. 1: connections for command bus 132 and address bus 134), an inherent activate command (when DRAM is selected for any operation, a write command (FIG. 3: receiving write command in step 302), and associated address information (FIG. 3: receiving address in step 302);
receiving, from the controller and via a data interface, data associated with the write command (FIG. 1: connections for DQ bus 136 for transmitting data);
calculating, based on the activate command, the write command, and the associated address information, CA parity information (FIG. 1: when CRC generator 150 generates CRC code for address separated from data, see 7:10-15);
calculating, based on the data associated with the write command, cyclical redundancy check (CRC) error checking information (FIG. 1: when CRC generator 150 generates CRC code for data separated from address, see 7:10-15);
calculating, based on the CA parity information and the CRC error checking information, error indicating information (FIG. 2B: e.g. modulating [An, Dn-k] or [An, Dn-k=1], see 6:66-7:9); and
transmitting, to the controller and via an error information interface, the error indicating information (FIG. 1: connections for EDC bus 138 for transmitting EDC information).
Regarding dependent claim 18, Shaeffer teaches wherein the associated address information includes a row address associated with the activate command and a column address associated with the write command (i.e. corresponding to row address and column address, see 3:34-43).
Allowable Subject Matter
Claims 19-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 19: the associated address information includes a first bank address associated with the activate command and a second bank address associated with the write command.
Response to Arguments
Applicant's arguments filed 01/09/2026 have been fully considered but they are not persuasive.
Applicant argues:
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Examiner disagrees that paragraph [0171] of Applicant’s specification draws a distinction between parity and CRC with phrase “… EDC calculation circuitry 1022a to calculate a parity or CRC value …” It is common knowledge that CRC involves parity principles and fundamentally based on the same concept of adding redundant parity-like bits. Parity is seen as a subset and CRC as a set, e.g. a single parity bit is a special case of a CRC. Even though the word “parity” does not appear in Schaeffer, the CRC generator 150 of FIG. 1 performs functions related to parity as known to skill in the art.
Examiner further clarify that when CRC generator 150 of FIG. 1 generates CRC code for address, it is seen as claimed CA parity error checking circuitry. When CRC generator 150 generates CRC code for data, it is seen as claimed data cyclical redundancy check (CRC) error checking circuitry.
Claims 2-18 maintain rejected for the reason set forth above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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February 18, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824