Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Min (US Pat. Pub. 2014/0220754)
Regarding claim 1, Min teaches a semiconductor device structure, comprising:
a first insulating layer formed over a semiconductor substrate [fig. 1, 12];
a plurality of conductive vias formed in the first insulating layer [fig.1, CT];
a plurality of conductive lines and a plurality of air gaps alternately formed over the first insulating layer, wherein the plurality of conductive lines correspondingly aligned to the plurality of conductive vias [fig. 1, conductive lines 50, air gaps 30, 50 are aligned to CT]; and
a plurality of capping layers correspondingly covering the plurality of air gaps [fig.1 ,40].
Regarding claim 2, Min discloses the semiconductor device structure as claimed in claim 1, further comprising a first liner cover sidewalls and bottom of each of the plurality of air gaps, wherein the first liner is made of an insulating material [fig.1, 20, paragraph [0057], silicon oxide taught].
Regarding claim 3, Min teaches the semiconductor device structure as claimed in claim 2, further comprising a second liner covering sidewalls and a bottom of each of the plurality of capping layers [fig. 1, 25].
Regarding claim 4, Min discloses the semiconductor device structure as claimed in claim 3, wherein the first liner is extending above the plurality of air gaps, so that the second liner is between each of the plurality of capping layers and the first liner [fig. 1, 20 extends above 30 and 25 is between 40 and 20].
Regarding claim 5, Min teaches the semiconductor device structure as claimed in claim 1, further comprising a plurality of second insulating layers correspondingly formed below the plurality of air gaps and over the first insulating layer [fig. 1, paragraph [0057] teaches 20 is silicon oxide, it can be interpreted as below the air gaps 30 and above first insulating layer 12].
Regarding claim 6, Min discloses the semiconductor device structure as claimed in claim 1, wherein an upper surface of the plurality of capping layers is substantially level with an upper surface of the plurality of conductive lines [fig. 1, the upper surface of 40 is level with the upper surface of 50].
Regarding claim 7, Min teaches a semiconductor device structure, comprising:
a first conductive line and a second conductive line formed over a semiconductor substrate [fig. 1, 50 on the far right of the figure and then next adjacent 50 can be first and second conductive line];
an air gap formed between a first sidewall surface of the first conductive line and a second sidewall surface the second conductive line [fig. 1, 30 between adjacent elements 50];
a top insulating layer capping a top of the air gap [fig. 1, 40]; and
a bottom insulating layer vertically spaced apart from the top insulating layer by the air gap [fig. 1, 12].
Regarding claim 8, Min discloses the semiconductor device structure as claimed in claim 7, further comprising:
an insulating liner conformally covering a top surface of the bottom insulating layer, the first sidewall surface of the first conductive line, and the second sidewall surface the second conductive line [fig. 1, 20].
Regarding claim 9, Min teaches the semiconductor device structure as claimed in claim 8, wherein the insulating liner is in direct contact with the first sidewall surface of the first conductive line and the second sidewall surface the second conductive line [fig. 1, 20 is in direct contact with sidewalls of adjacent conductive lines 50].
Regarding claim 10, Min discloses the semiconductor device structure as claimed in claim 8, wherein a top surface of the insulating liner is substantially level with a top surface of the top insulating layer [fig. 1, a top surface of 20 is level with a top surface of 40].
Regarding claim 11, Min teaches the semiconductor device structure as claimed in claim 7, further comprising:
a first insulating liner conformally covering a bottom surface and two opposite sidewall surfaces of the top insulating layer [fig. 1, 25].
Regarding claim 12, Min discloses the semiconductor device structure as claimed in claim 11, further comprising:
a second insulating liner conformally covering a top surface of the bottom insulating layer and separating the first insulating liner from the first conductive line and from the second conductive line [fig. 1, 20].
Regarding claim 13, Min teaches the semiconductor device structure as claimed in claim 12, wherein a top surface of the first insulating liner is substantially level with a top surface of the top insulating layer and a top surface of the second insulating liner [fig. 1, a top surface 25 is level with a top surface of 40 and top surface of 20].
Regarding claim 14, Min discloses the semiconductor device structure as claimed in claim 7, wherein a width of the top insulating layer is small than a width of the bottom insulating layer [fig. 1, the width of 40 is less than the width of 12].
Regarding claim 15, Min teaches a semiconductor device structure, comprising:
a conductive feature having a first portion embedded in an insulating layer and a second portion formed on top surfaces of the first portion and the insulating layer [fig. 1, CT and 50 formed on top surfaces of CT];
a first space structure formed adjacent to a first sidewall surface of the second portion [fig. 1, 20/30/25 to the left side of one of the elements 50]; and
a second space structure formed adjacent to a second sidewall surface of the second portion, wherein the second sidewall surface is opposite to the first sidewall surface [fig. 1, 20/30/25 on the right side of element 50 that has 30 on the left], wherein the first space structure and the second space structure each comprises:
an air gap [fig. 1, 30];
a first insulating liner defining two opposite sidewalls and a bottom of the air gap [fig. 1, 20]; and
a second insulating liner capping a top of the air gap and covered by the first insulating liner [ fig. 1, 25 caps the top of 30 and is covered on three sides by 20].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min as applied to claims 1-15 above, and further in view of Hsieh (US Pat. Pub. 202/0258772).
Regarding claim 16, Min fails to teach a bottom layer formed between the insulating layer and a portion of the first insulating layer that defines the bottom of the air gap. However, Hsieh teaches a plurality of conductive structures with air gaps adjacent to said structures, the air gaps having a liner and a bottom layer between an insulating layer and the liner [fig. 1, air gaps 201, conductive structures 210, liner 220, bottom layer 230].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Hsieh into the method of Min by forming a bottom layer between the insulating layer and a portion of the first insulating liner that defines the bottom of the air gap. The ordinary artisan would have been motivated to modify Min in the manner set forth above for at least the purpose of utilizing a layer that strengthens attachment of overlying films and provides additional protection to the conductive elements [Hsieh, paragraph [0058]].
Regarding claim 17, Min in view of Hsieh discloses the semiconductor device structure as claimed in claim 16, wherein an interface between the bottom layer and the insulating layer is substantially level with an interface between the first portion of the conductive feature and the second portion of the conductive feature [Min, fig. 1, a bottom layer being present between the liner and the insulating layer would have an interface level with the interface between 50 and CT].
Regarding claim 18, Min in view of Hsieh teaches the semiconductor device structure as claimed in claim 16, wherein the first space structure and the second space structure each comprises:
a top layer separated the air gap and the first insulating liner by the second insulating liner [Min, fig. 1, 40, separated from the air gap and the first liner by the second liner 25].
Regarding claim 19, Min in view of Hsieh discloses the semiconductor device structure as claimed in claim 18, wherein a top surface of the top layer is substantially level with a top surface of the second portion of the conductive feature [Min, fig. 1, top surface of 40 is level with a top surface of 50].
Regarding claim 20, Min in view of Hsieh teaches the semiconductor device structure as claimed in claim 18, wherein the top layer and the bottom layer have different widths [Min, fig. 1, top layer has a first width and a bottom layer being present between the first insulating layer and the insulating layer would have a second width greater than the first].
Conclusion
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/JOHN M PARKER/Primary Examiner, Art Unit 2899
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