DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election
Claims #16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 8, 2026.
IDS
The IDS document(s) filed on April 29, 2024 has been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Rejections – 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-4, 6-9, 11-13 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
As to claims 2 and 11, it is unclear whether “a common footprint” is referring to a structural limitation or a process limitation. Here, Applicant’s published specification paragraphs [0062], [0065] favor a process limitation interpretation because the common footprint is defined by patterning the top plate and first bottom plate, together with the capacitor dielectric, using a same mask. If “common footprint” instead refers to a structural limitation then it is further unclear what structure constitutes the common footprint. While published specification [0065] and FIG. 7B teach the common footprint includes the first bottom plate 450, the capacitor dielectric 452, and the top plate 454, it is unclear how “the bottom plate and the top plate have a common footprint”, e.g. how the constituent parts have a combined part.
The Examiner instead assumes the common footprint refers to layers 450+452+454 having a monolithic structure in which lateral sides are aligned/flush with one another.
As to claims 6-9, it is unclear how the capacitor dielectric 452 defines a gap 702 when the gap is formed in the top plate 454 in FIG. 10. The Examiner assumes the gap is formed within/at least partially surrounded by both the capacitor dielectric and top plate layers.
Claim Rejections 35 U.S.C. § 102(a)(1)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Seidel et al. (U.S. Patent Publication No. 2020/0135845 A1), as cited in the IDS and hereafter “Seidel”.
As to claim 1, Seidel teaches:
A dielectric layer 122 defining a plurality of trenches 155. See Seidel, FIG. 1A.
A bottom plate 151 of conductive material overlying the dielectric layer and lining sides of the plurality of trenches.
A capacitor dielectric 152 directly overlying the bottom plate and extending into the plurality of trenches.
A top plate 153 of conductive material directly overlying the capacitor dielectric.
A metal layer 172 overlying and directly contacting the top plate.
As to claim 2, per the Examiner’s 35 U.S.C. § 112(b) rejection interpretation above, Seidel teaches the bottom plate and the top plate have a common footprint, i.e. a monolithic structure in which lateral sides are aligned/flush with one another. Id.
As to claim 3, Seidel teaches a passivation layer 123 partially overlying the top plate, and wherein the passivation layer further extends around a right edge of the common footprint to provide electrical isolation between the metal layer and the bottom plate. Id.
As to claim 4, Seidel teaches a spacer 123 of insulating material covering a right edge of the common footprint. Id.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the later invention.
Claims 10-13, 15 are rejected under 35 U.S.C. § 103 as being unpatentable over Seidel, and further in view of Lee et al. (U.S. Patent Publication No. 2023/0067249 A1), hereafter “Lee”.
As to claim 10, Seidel teaches:
A dielectric layer 122. See Seidel, FIG. 1A.
A bottom plate 151 of conductive material overlying the dielectric layer.
A capacitor dielectric 152 directly overlying the bottom plate.
A top plate 153 of conductive material directly overlying the capacitor dielectric.
An interconnect layer 172 overlying and directly contacting the top plate.
However, Seidel does not teach, inter alia, a pixel array, a plurality of image sensor pixels, and a photodetector.
On the other hand, Lee teaches a pixel array such as a CMOS image sensor comprising a plurality of image sensor pixels, i.e. pixel sensors, wherein each of the image sensor pixels 101a includes a photodetector 103 and a metal-insulator-metal capacitor 120. See Lee, ¶ [0015], FIG. 3A.
It would have been obvious to one of ordinary skill in the art to incorporate the capacitor structure as taught by Seidel into the pixel array including image sensor pixels, a photodetector, and capacitors as taught by Lee, in order to yield the predictable benefit of achieving noise reduction in decoupling capacitors. Id. at ¶¶ [0001], [0015].
As to claim 11, per the Examiner’s 35 U.S.C. § 112(b) rejection interpretation above, Seidel teaches the bottom plate and the top plate have a common footprint, i.e. a monolithic structure in which lateral sides are aligned/flush with one another. See Seidel, FIG. 1A.
As to claim 12, Seidel teaches a passivation layer 123 partially overlying the top plate, and wherein the passivation layer further extends around a right edge of the common footprint. Id.
As to claim 13, Seidel teaches a spacer 123 of insulating material covering a right edge of the common footprint. Id.
As to claim 15, Lee teaches a vehicle such as digital cameras or optical imaging devices. See Lee, ¶ [0001]. The Examiner is interpreting “vehicle” as a container. The Examiner notes Applicant has not specified a motor vehicle, and assuming arguendo, this would be an exceedingly obvious application.
Claim 7 is rejected under 35 U.S.C. § 103 as being unpatentable over Seidel, and further in view of Cheng et al. (U.S. Patent Publication No. 2020/0066922 A1), hereafter “Cheng”.
As to claim 7, Seidel does not teach inter alia the capacitor dielectric defines a gap.
On the other hand, Cheng teaches a gap 112/202 formed within/partially surrounded by the capacitor dielectric 108 and top plate (top most 106), per the Examiner’s 35 U.S.C. § 112(b) rejection above. See Cheng, FIG. 1, FIG. 2B. Cheng further teaches the gap within at least one trench of the plurality of trenches, wherein the gap defines a hole with no solid material therein. Id.
It would have been obvious to one of ordinary skill in the art to incorporate the gap as taught by Cheng into the overall trench capacitor as taught by Seidel, in order to yield the predictable result of absorbing stresses. Id. at ¶ [0026].
Claims Allowable If Rewritten in Independent Form
Claims 5 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 5 and 14, while Friedrich et al. (U.S. Patent Publication No. 2015/0061069 A1), hereafter “Friedrich”, teaches in FIG. 1J a capacitor dielectric 46 extending beyond a periphery of a bottom plate 42, Friedrich does not teach or suggest a motivation for the combination nor was the Examiner able to provide a motivation.
No Prior Art Applied
No prior art has been applied to claims 6, 8, and 9 because Cheng does not teach the top plate (top most 106) extending into the gap 112 as recited by claim 6 nor the gap 112 filled by a metal material of the metal layer as recited by claim 8 nor the passivation layer extending into the gap as recited by claim 9.
Prior Art Not Relied Upon
The following prior art was not relied upon but is made of record:
Lin (U.S. Patent Publication No. 2016/0020267 A1)
Conclusion
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/SUBERR L CHI/Primary Examiner, Art Unit 2893