DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karnezos (US 2004/0195667).
Regarding claim 1, Karnezos teaches (fig. 6A - 6C):
A semiconductor package, comprising:
a substrate (52) having a substrate surface, wherein the substrate comprises conductive patterns on the substrate surface;
a first semiconductor die (421) attached onto the substrate surface;
a heat spreader (626) mounted over and thermally coupled to the first semiconductor die, wherein the heat spreader comprises an overhanging portion that extends laterally beyond the first semiconductor die, wherein the overhanging portion has a spreader bottom surface facing towards the substrate surface (FIG. 6C);
at least one second semiconductor die (32) attached onto the spreader bottom surface of the overhanging portion and beneath the overhanging portion of the heat spreader, wherein the at least one second semiconductor die is thermally coupled to the overhanging portion of the heat spreader, and is electrically coupled to at least one of the conductive patterns of the substrate (FIG. 6C); and
an encapsulant layer (617) encapsulating the first semiconductor die, the at least one second semiconductor die, the heat spreader and the conductive patterns on the substrate surface.
Regarding claim 2, Karnezos teaches:
The semiconductor package of claim 1, wherein the at least one second semiconductor die is attached onto the spreader bottom surface of the overhanging portion via a thermal interface material or a die adhesive film (615).
Regarding claim 3, Karnezos teaches:
The semiconductor package of claim 1, wherein the heat spreader is mounted over and thermally coupled to the first semiconductor die via a thermal interface material or a die adhesive film (613).
Regarding claim 4, Karnezos teaches:
The semiconductor package of claim 1, further comprising: at least one electronic component (36) attached onto the substrate surface and besides the first semiconductor die, wherein the at least one electronic component is under the at least one second semiconductor die (FIG. 6C).
Regarding claim 5, Karnezos teaches:
The semiconductor package of claim 1, wherein the overhanging portion of the heat spreader extends horizontally with respect to the substrate surface (FIG. 6C).
Regarding claim 6, Karnezos teaches:
The semiconductor package of claim 1, wherein the overhanging portion of the heat spreader is inclined towards the substrate surface (notches 625).
Regarding claim 7, Karnezos teaches:
The semiconductor package of claim 1, wherein the at least one second semiconductor die is electrically coupled to the at least one of the conductive patterns on the substrate surface via wire bonding (516).
Regarding claim 8, Karnezos teaches:
The semiconductor package of claim 1, wherein a top surface of the at least one second semiconductor die comprises an exposed portion from the spreader bottom surface of the overhanging portion, wherein the exposed portion comprises at least one conductive structure for electrically coupling to the at least one of the conductive patterns of the substrate (FIG. 6C).
Regarding claim 9, Karnezos teaches (FIG. 6A – 6C):
A method for forming a semiconductor package, comprising:
providing a substrate (52) having a substrate surface, wherein the substrate comprises conductive patterns formed on the substrate surface and a first semiconductor die (421) attached onto the substrate surface;
providing a heat spreader (626) having a spreader bottom surface and at least one second semiconductor die (32), wherein the at least one second semiconductor die is attached onto the spreader bottom surface (FIG. 6A);
attaching the heat spreader onto the first semiconductor die such that a portion of the heat spreader attached with the at least one second semiconductor die overhangs from the first semiconductor die (FIG. 6C);
forming at least one electrical connection (516) to electrically connect the at least one second semiconductor die with at least one of the conductive patterns of the substrate; and
forming an encapsulant layer (617) on the substrate to encapsulate the first semiconductor die, the at least one second semiconductor die, the heat spreader, the at least one electrical connection and the conductive patterns of the substrate.
Regarding claim 10, Karnezos teaches:
The method of claim 9, wherein providing a heat spreader having a spreader bottom surface and at least one second semiconductor die comprises: attaching the at least one second semiconductor die onto the spreader bottom surface via a thermal interface material or a die adhesive film (615).
Regarding claim 11, Karnezos teaches:
The method of claim 9, wherein attaching the heat spreader onto the first semiconductor die comprises: forming a thermal interface material or a die adhesive film on the first semiconductor die; and attaching the heat spreader onto the first semiconductor die via the thermal interface material or the die adhesive film (613).
Regarding claim 12, Karnezos teaches:
The method of claim 9, further comprising: attaching at least one electronic component (36) onto the substrate surface of the substrate and besides the first semiconductor die, wherein upon attaching the heat spreader onto the first semiconductor die, the at least one electronic component is under the at least one second semiconductor die (FIG. 6C).
Regarding claim 13, Karnezos teaches:
The method of claim 9, wherein upon attaching the heat spreader onto the first semiconductor die, the portion of the heat spreader overhanging from the first semiconductor die extends horizontally with respect to the substrate surface (FIG. 6C).
Regarding claim 14, Karnezos teaches:
The method of claim 9, wherein upon attaching the heat spreader onto the first semiconductor die, the portion of the heat spreader overhanging from the first semiconductor die is inclined towards the substrate surface (notch 625).
Regarding claim 15, Karnezos teaches:
The method of claim 9, wherein forming at least one electrical connection to electrically connect the at least one second semiconductor die with at least one of the conductive patterns of the substrate comprises: forming at least one bonding wire (516) to electrically connect the at least one second semiconductor die with the at least one of the conductive patterns of the substrate.
Regarding claim 16, Karnezos teaches:
The method of claim 9, wherein providing a heat spreader having a spreader bottom surface and at least one second semiconductor die comprises: attaching a first portion of a top surface of the at least one second semiconductor die onto the spreader bottom surface, wherein a second portion of the top surface of the at least one second semiconductor exposed from the spreader bottom surface has at least one conductive structure formed thereon (FIG. 6A).
Regarding claim 17, Karnezos teaches:
The method of claim 16, wherein forming at least one electrical connection to electrically connect the at least one second semiconductor die with at least one of the conductive patterns of the substrate comprises: forming at least one electrical connection to electrically connect the conductive structure formed on the second portion of the top surface of the at least one second semiconductor with the at least one of the conductive patterns of the substrate (516, FIG. 6C).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624
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