Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Currently, claims 1-12 are pending and examined below.
Information Disclosure Statement (IDS)
Two information disclosure statements submitted on 07/16/2025 ("07-16-25 IDS") and 10/15/2025 (“10-15-25 IDS”) are in compliance with the provisions of 37 CFR 1.97. Accordingly, the 07-16-25 IDS and 10-15-25 IDS are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND TESTING MODULES WITHIN SCRIBE LINE AND METHOD FOR MANUFACTURING THE SAME
A. Prior-art rejections based on Choi
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2021/0175133 A1 to Choi et al. ("Choi").
Figs. 7 and 1 of Choi have been annotated to support the rejection below:
[AltContent: textbox (49A3)][AltContent: arrow][AltContent: textbox (D2)][AltContent: arrow][AltContent: arrow][AltContent: textbox (AR2)][AltContent: textbox (AR1)]
PNG
media_image1.png
514
510
media_image1.png
Greyscale
[AltContent: textbox (45)][AltContent: textbox (D3)][AltContent: arrow][AltContent: arrow][AltContent: textbox (AR1)][AltContent: textbox (AR2)]
PNG
media_image2.png
275
435
media_image2.png
Greyscale
Regarding independent claim 1, Choi teaches a semiconductor device (para [0032] - “FIG. 1 may be a cross-sectional view taken along line I-I′ of FIG. 7. FIG. 2 may be a cross-sectional view taken along line II-II′ of FIG. 7”), comprising:
a first active region AR1 and a second active region AR2 separated by the first active region AR1 by a scribe line SL1, wherein the scribe line SL1 extends along a first direction D1;
a first testing module 49A (para [0033] - “For example, the substrate 21 may include a plurality of chip regions CH and a first scribe lane SL1, and the wafer may include a first pattern group 49A, a second pattern group 49B…”) abutting the first active region AR1 and disposed within the scribe line SL1; and
a second testing module 49B abutting the second active region AR2 and disposed within the scribe line SL1,
wherein the first testing module 49A and the second testing module 49B are arranged along a second direction D2 substantially orthogonal to the first direction D1.
Regarding claim 2, Choi teaches the first testing module 49A that comprises a first testing pad 45 and a first testing circuit 41 or 41, 42, 43, 44 (para [0037] - “a plurality of middle wirings 44, a plurality of middle plugs 43, a lower plug 42, and a test pattern 41. The test pad 45, the plurality of middle wirings 44, the plurality of middle plugs 43, the lower plug 42, and the test pattern 41 may form the TEG for assessing electric properties of elements constituting an integrated circuit chip (e.g., the chip regions CH).”) arranged along the first direction D1.
Regarding claim 3, Choi teaches the second testing module 49B that comprises a second testing pad 45 and a second circuit 41 or 41, 42, 43, 44 arranged along the first direction D1.
Regarding claim 4, Choi teaches the second testing pad 45 is aligned with the first testing pad 45 along the second direction D2.
Regarding claim 5, Choi teaches the second testing pad 45 that is aligned with the first testing circuit 41 or 41, 42, 43, 44 along the second direction D2.
Regarding claim 6, Choi teaches the scribe line SL1 that comprises a cutting region SLC1 (para [0041] - “The first division region SLC1”) between the first testing module AR1 and the second testing module AR2.
Regarding claim 7, Choi teaches the first testing module 49A that comprises a via structure 42 connecting the first testing pad 45 and the first testing circuit 41, and the via structure 42 is free from overlapping the cutting region SLC1 along a third direction D3 substantially perpendicular to the first direction D1 and the second direction D2.
Regarding claim 8, Choi teaches the first testing pad 45 is free from overlapping the cutting region SLC1 along a third direction D3 substantially perpendicular to the first direction D1 and the second direction D2.
Regarding claim 9, Choi teaches the first testing circuit 41 or 41, 42, 43, 44 that is free from overlapping the cutting region SLC1 along a third direction D3 substantially perpendicular to the first direction D1 and the second direction D2.
Regarding claim 10, Choi teaches the cutting region SLC1 that is free of metallic materials (see Fig. 1).
Regarding claim 11, Choi teaches the first testing module 49A that comprises a via structure 42 connecting the first testing pad 45 and the first testing circuit 41 or 41, 42, 43, 44, and the via structure 42 that is closer to the first active region AR1 than the first testing circuit 41 or 41, 42, 43, 44 is.
Regarding claim 13, Choi teaches a third testing module 49A3, wherein the first testing module 49A and the third testing module 49A3 are arranged along the first direction D1.
B. Prior-art rejections based on Daubenspeck
Claim Rejections - 35 USC § 102
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2014/0319522 A1 to Daubenspeck et al. ("Daubenspeck").
Figs. 4 and 5 of Daubenspeck have been annotated to support the rejection
below:
[AltContent: textbox (CR)][AltContent: arrow][AltContent: connector][AltContent: textbox (TM3 (TP3))][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (AR2)][AltContent: arrow][AltContent: textbox (AR1)][AltContent: arrow][AltContent: textbox (TM2 (TP2))][AltContent: textbox (TM1 (TP1))][AltContent: textbox (D1)][AltContent: textbox (D2)][AltContent: arrow][AltContent: arrow]
PNG
media_image3.png
382
378
media_image3.png
Greyscale
[AltContent: textbox (TP)][AltContent: arrow][AltContent: textbox (TM1)][AltContent: arrow][AltContent: rect][AltContent: textbox (V1)][AltContent: arrow]
PNG
media_image4.png
382
555
media_image4.png
Greyscale
Regarding independent claim 1, Daubenspeck teaches a semiconductor device (see Fig. 5, for example), comprising:
a first active region AR1 (Fig. 4 shows four active regions 210. One of the four active regions has been annotated as AR1.) and a second active region AR2 separated by the first active region AR1 by a scribe line 220 (para [0049] - “kerf region 220”), wherein the scribe line 220 extends along a first direction D1; and
a first testing module TM1 (para [0050] - “one or more testing structures 221 for performing wafer-level testing of the integrated circuit chip…However, it should be understood that the devices 211 can comprise any number of suitable integrated circuit devices (e.g., planar field effect transistors, non-planar field effect transistors, bipolar transistors, capacitors, diodes, etc.), according to the design of the integrated circuit chip. Similarly, the test structures 221 can comprise any number of suitable test devices (e.g., planar field effect transistors, non-planar field effect transistors, bipolar transistors, capacitors, diodes, etc.) or parametric measurement macros suitable for wafer-level testing of the integrated circuit chips, as designed.”) abutting the first active region AR1 and disposed within the scribe line 220,
a second testing module TM2 abutting the second active region AR2 and disposed within the scribe line 220,
wherein the first testing module TM1 and the second testing module TM2 are arranged along a second direction D2 substantially orthogonal to the first direction D1.
Regarding claim 2, Daubenspeck teaches the first testing module TM1 that comprises
a testing pad TP (para [0052] - “additional metal interconnect(s) 217 can also be formed within the stack 202. Each additional metal interconnect 217 comprise, for example, an additional combination of metal wires and vias that extend from a test structure 221 in a kerf region 220 of the semiconductor layer 201 to the top surface 203 of the stack 202.”) and a
a first testing circuit 221 arranged along the first direction D1.
Regarding claim 3, Daubenspeck teaches the second testing module TM2 that comprises a second testing pad TP2 (217) and a second testing circuit 221 along the first direction D1.
Regarding claim 4, Daubenspeck teaches the second testing pad TP2 (217) that is aligned with the first testing pad TP1 along the second direction D2.
Regarding claim 5, Daubenspeck teaches the second testing pad TP2 that is (partially) aligned with the first testing circuit 221 along the second direction D2.
Regarding claim 6, Daubenspeck teaches the scribe line 220 that comprises a cutting region CR between the first testing module TM1 and the second testing module TM2.
Regarding claim 7, Daubenspeck teaches the first testing module TM1 that comprises a via structure V1 connecting the first testing pad TP1 and the first testing circuit 221, and the via structure V1 is free from overlapping the cutting region CR along a third direction substantially perpendicular to the first direction D1 and the second direction D2.
Regarding claim 8, the first testing pad TP1 that is free from overlapping the cutting region CR along a third direction D3 substantially perpendicular to the first direction D1 and the second direction D2.
Regarding claim 9, the first testing circuit 221 that is free from overlapping the cutting region CR along a third direction substantially perpendicular to the first direction D1 and the second direction D2.
Regarding claim 10, Daubenspeck teaches the cutting region CR that is free of metallic materials.
Regarding claim 11, Daubenspeck teaches the first testing module TM1 that comprises a via structure V1 connecting the first testing pad TP1 and the first testing circuit 221, and the via structure V1 that is closer to the first action region AR1 than the first testing circuit 221 is.
Regarding claim 12, Daubenspeck teaches a third testing module TM3, wherein the first testing module TM1 and the third testing module TM3 that are arranged along the first direction D1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2019/0139841 A1 to Stamper et al.
Pub. No. US 2014/0167199 A1 to Cheng et al.
Pub. No. US 2013/0221353 A1 to Yang et al.
Pub. No. US 2010/0207251 A1 to Yu et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 09 June 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status
Prosecution Insights