DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-9) in the reply filed on 9/1/2026 is acknowledged.
Claim 10 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/1/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Iwai et al (US Publication No. 2023/0232624) in view of Lee et al (US Publication No. 2022/0093532).
Regarding claim 1, Iwai discloses a semiconductor device with decreased source and drain resistance, comprising: a substrate Fig 7A, 10; and a plurality of three-dimensional semiconductor device arrays Fig 12A, wherein the three-dimensional semiconductor device arrays are provided on the substrate Fig 12A, and the three-dimensional semiconductor device arrays are separated by isolation grooves Fig 6A, 41/43 wherein each of the three-dimensional semiconductor device arrays comprises a plurality of device layers in a vertical direction Fig 7A, each of the device layers Fig 19A-19B comprises a stack of a source/drain layer Fig 12A, 19A-19B, a channel layer and a source/drain layer Fig 12A, 19A-19B, and wherein the three-dimensional semiconductor device array further comprises a plurality of gate stacks arranged in an array Fig 12A, 17-19B, the gate stack penetrates each of the device layers in the vertical direction and comprises a gate material and a gate dielectric layer provided between the gate material and the device layer ¶0099-0101, and a device unit is defined at an intersection of the gate stack and the device layer Fig 12A, 17-19B. Iwai discloses all the limitations but silent on the isolation groove.
Whereas Lee discloses a semiconductor device with decreased source and drain resistance, comprising: a substrate Fig 25, Sub; and a plurality of three-dimensional semiconductor device arrays Fig 19, wherein the three-dimensional semiconductor device arrays are provided on the substrate Fig 19 ¶0130-0132, and the three-dimensional semiconductor device arrays are separated by isolation grooves Fig 25, SPC1; wherein each of the three-dimensional semiconductor device arrays comprises a plurality of device layers in a vertical direction, each of the device layers Fig 20-25 comprises a stack of a source/drain layer, a channel layer and a source/drain layer, and an end face of the source/drain layer ¶0110-0111 adjacent to the isolation groove is metallized to form a silicide Fig 26 ¶0159-0160; and wherein the three-dimensional semiconductor device array further comprises a plurality of gate stacks arranged in an array Fig 21-26. Iwai and Lee are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Iwai because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Iwai and incorporate the teachings of Lee to improve device insulation.
Regarding claim 2, Lee discloses wherein the source/drain layer and the channel layer in each of the device layers extend in a direction in which the isolation groove extends Fig 21-26, While Iwai discloses a staircase like contact region is formed at the source/drain layer Fig 12A, 17-19B.
Regarding claim 3, Iwai discloses wherein a silicon dioxide is deposited on the three-dimensional semiconductor device array to form a dielectric isolation layer ¶0061, 0115 which covers a contact region and an upper surface of the three-dimensional semiconductor device array as well as each isolation groove, and an upper surface of the dielectric isolation layer is flattened Fig 17.
Regarding claim 4, Iwai discloses wherein vertically etching is performed downwards from the upper surface of the dielectric isolation layer to form a plurality of contact holes, and each of the contact holes extends to the contact region of the source/drain layer Fig 9A.
Regarding claim 5, Iwai discloses wherein a lower source/drain layer in an upper device layer and an upper source/drain layer in a lower device layer adjacent to the upper device layer are the same source/drain layer Fig 19A-19C.
Regarding claim 6, Iwai discloses wherein a silicon dioxide isolation layer is provided between two source/drain layers of each device layer and at a bottom of the three-dimensional semiconductor device array; wherein a bottom of the gate stack is located in the silicon dioxide isolation layer at the bottom of the three-dimensional semiconductor device array; and wherein the channel layer is provided between the gate dielectric layer and a structure formed by the two source/drain layers and the silicon dioxide isolation layer Fig 12A, 17-19B.
Regarding claim 7, Lee discloses wherein each of the source/drain layer and the channel layer is made of a doped polycrystalline silicon material ¶0047.
Regarding claim 8, Iwai discloses wherein an upper surface of the substrate is provided with a silicon germanium layer ¶0046; wherein a bottom of the gate stack is located in the silicon germanium layer; wherein the source/drain layer, the channel layer and the source/drain layer in the device layer are stacked sequentially from bottom to top; wherein a bottom of the isolation groove is located in the silicon germanium layer; and wherein a dielectric inner spacer is formed at each of an end face of the channel layer adjacent to the isolation groove and an end face of the silicon germanium layer adjacent to the isolation groove Fig 12A, 17-19B..
Regarding claim 9, Iwai and Lee disclose wherein the source/drain layer is made of a heavily doped silicon material, and the channel layer is made of a silicon germanium material Iwai ¶0106, 0134-0135 Lee ¶0047.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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