DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 2018/0122703) (hereafter Cheng).
Regarding claim 1, Cheng discloses a semiconductor device, comprising:
a substrate 102 (Fig. 18, paragraph 0033);
a raised region (element number is not shown in Fig. 18 but see1702a in Fig. 17) disposed on the substrate 102 (Fig. 18);
a nanostructured channel region (element number is not shown in Fig. 18 but see 1702b and 1702c in Fig. 17) disposed on the raised region (element number is not shown in Fig. 18 but see1702a in Fig. 17);
a source/drain (S/D) region (1402a, 1402b, and 1042c in Fig. 18 and paragraph 0056) disposed adjacent to the nanostructured channel region (element number is not shown in Fig. 18 but see 1702b and 1702c in Fig. 17);
a first gate structure 1801b (Fig. 18, paragraph 0064) extending through the nanostructured channel region (element number is not shown in Fig. 18 but see 1702b and 1702c in Fig. 17) and disposed on the raised region (element number is not shown in Fig. 18 but see1702a in Fig. 17); and
a second gate structure (1801a and 1801c in Fig. 18, paragraph 0064) surrounding the first gate structure 1801b (Fig. 18) and the nanostructured channel region (element number is not shown in Fig. 18 but see 1702b and 1702c in Fig. 17), wherein top surfaces of the first 1801b (Fig. 18) and second gate structures 1801a and 1801c in Fig. 18) are substantially coplanar with each other.
Regarding claim 2, Cheng further discloses the semiconductor device of claim 1, wherein a gate dielectric layer (element number is not shown in Fig. 18 but see right 702 in Fig. 12 and paragraph 0049) of the first gate structure 1801b (Fig. 18) is in contact with a gate dielectric layer (element number is not shown in Fig. 18 but see left 702 in Fig. 12 and paragraph 0049) of the second gate structure (1801a and 1801c in Fig. 18).
Regarding claim 3, Cheng further discloses the semiconductor device of claim 1, wherein a gate dielectric layer (1802 of 1801a and 1802 of 1801c in Fig. 18, paragraph 0064) of the second gate structure (1801a and 1801c in Fig. 18) is disposed concentrically around a gate dielectric layer (1802 of 1801b in Fig. 18, paragraph 0064) of the first gate structure 1801b (Fig. 18).
Regarding claim 5, Cheng further discloses the semiconductor device of claim 1, wherein the first gate structure 1801b (Fig. 18) comprises: a conductive layer (1806 of 1801b in Fig. 18) extending through the nanostructured channel region (element number is not shown in Fig. 18 but see 1702b and 1702c in Fig. 17); and a dielectric layer (1802 of 1801b in Fig. 18, paragraph 0064) disposed concentrically around the conductive layer (1806 of 1801b in Fig. 18).
Regarding claim 7, Cheng further discloses the semiconductor device of claim 1, wherein the second gate structure (1801a and 1801c in Fig. 18, paragraph 0064) surrounds the first gate structure 1801b (Fig. 18) about a first axis and surrounds the nanostructured channel region (element number is not shown in Fig. 18 but see 1702b and 1702c in Fig. 17) about a second axis different from the first axis.
Regarding claim 8, Cheng further discloses the semiconductor device of claim 1, wherein: the first gate structure 1801b (Fig. 18) comprises a dielectric layer 1502 (Fig. 18, paragraph 0060), the second gate structure (1801a and 1801c in Fig. 18) comprises a silicon oxide layer (element number is not shown in Fig. 18 but see 802 in Fig. 8, paragraph 0050; and see paragraph 0049, wherein “silicon oxide”) and a high-k dielectric layer (1802 of 1801a and 1802 of 1801c in Fig. 18, paragraph 0064), and the dielectric layer 1502 (Fig. 18) is in contact with sidewalls of the silicon oxide layer (element number is not shown in Fig. 18 but see 802 in Fig. 8, paragraph 0050; and see paragraph 0049, wherein “silicon oxide”) and the high-k dielectric layer (1802 of 1801a and 1802 of 1801c in Fig. 18).
Regarding claim 9, Cheng discloses the semiconductor device of claim 1, however Cheng does not disclose an etch stop layer 1502 (Fig. 18, paragraph 0060) disposed on the S/D region (1402a, 1402b, and 1042c in Fig. 18 and paragraph 0056), wherein top surfaces of the etch stop layer 1502 (Fig. 18) and the first gate structure 1801b (Fig. 18) are substantially coplanar.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 1 above, and further in view of Ching et al. (US 2019/0237464) (hereafter Ching).
Regarding claim 4, Cheng discloses the semiconductor device of claim 1, however Cheng does not disclose a negative capacitance dielectric layer of the first gate structure is disposed concentrically around a negative capacitance dielectric layer of the second gate structure.
Ching discloses a negative capacitance dielectric layer (leftmost 604 and rightmost 604 in Fig. 10A, paragraph 0040) of the first gate structure (leftmost 1002 and rightmost 1002 in Fig. 10A, paragraph 0054) is disposed concentrically around a negative capacitance dielectric layer (middle 604 in Fig. 10A, paragraph 0040) of the second gate structure (middle 1002 in Fig. 10A, paragraph 0054).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng to form a negative capacitance dielectric layer of the first gate structure is disposed concentrically around a negative capacitance dielectric layer of the second gate structure, as taught by Ching, since the composition of the high-k dielectric layer 602 (Ching, Fig. 11B, paragraph 004) and the ferroelectric insulator layer 604 (Ching, Fig. 11B, paragraph 004) are selected such as together the layers are operable to provide for a negative-capacitance FET, when a gate electrode is formed thereover.
Regarding claim 6, Cheng further discloses the semiconductor device of claim 1, wherein the first gate structure 1801b (Fig. 18) comprises: a conductive layer (1806 of 1801b in Fig. 18) extending through the nanostructured channel region (element number is not shown in Fig. 18 but see 1702b and 1702c in Fig. 17).
Cheng does not disclose a negative capacitance dielectric layer disposed concentrically around the conductive layer; and a high-k dielectric layer disposed concentrically around the negative capacitance dielectric layer.
Ching discloses a negative capacitance dielectric layer 604 (Fig. 10B, paragraph 0040) disposed concentrically around the conductive layer 1006 (Fig. 10B, paragraph 0054); and a high-k dielectric layer 602 (Fig. 10B, paragraph 0054) disposed concentrically around the negative capacitance dielectric layer 604 (Fig. 10B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng to form a negative capacitance dielectric layer disposed concentrically around the conductive layer; and a high-k dielectric layer disposed concentrically around the negative capacitance dielectric layer, as taught by Ching, since the composition of the high-k dielectric layer 602 (Ching, Fig. 11B, paragraph 004) and the ferroelectric insulator layer 604 (Ching, Fig. 11B, paragraph 004) are selected such as together the layers are operable to provide for a negative-capacitance FET, when a gate electrode is formed thereover.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng as applied to claim 1 above, and further in view of Kang et al. (US 2022/0108989) (hereafter Kang).
Regarding claim 10, Cheng discloses the semiconductor device of claim 1, however Cheng does not disclose a first conductive structure disposed on the first gate structure; and a second conductive structure disposed on the second gate structure.
Kang discloses a first conductive structure (second CB from the left corner of Fig. 19, paragraph 0089) disposed on the first gate structure (second 542 and second 545 from the left corner of Fig. 19, paragraph 0163); and a second conductive structure (first CB and third CB from the left corner of Fig. 19, paragraph 0089) disposed on the second gate structure (first 542, third 542, first 545, and third 545 from the left corner of Fig. 19, paragraph 0163).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng to form a first conductive structure disposed on the first gate structure; and a second conductive structure disposed on the second gate structure, as taught by Kang, since the gate contacts CB (Kang, Fig. 19, paragraph 0090) may be disposed on a plurality of gate lines GS (Kang, Fig. 19, paragraph 0090) to connect the plurality of gate lines GS (Kang, Fig. 19, paragraph 0090) and other devices.
Claims 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Gwon et al. (US 2021/0035976) (hereafter Gwon), in view of Noh et al. (US 2022/0085161) (hereafter Noh).
Regarding claim 11, Gwon discloses a semiconductor device, comprising:
a substrate 100 (Fig. 2, paragraph 0031);
a nanostructured channel region 115 (Fig. 2, paragraph 0039) disposed on the substrate 100 (Fig. 2);
first (120 in Fig. 2, paragraph 0030) and second gate structures (220 in Fig. 2, paragraph 0030) extending through the nanostructured channel region 115 (Fig. 2) and disposed on the substrate 100 (Fig. 2); and
a third gate structure (130, 120_1, 220_1, and 230 in Fig. 2, paragraph 0053) surrounding the first (120 in Fig. 2) and second gate structures (220 in Fig. 2) and the nanostructured channel region 115 (Fig. 2).
Gwon does not disclose diameters of the first and second gate structures are different from each other.
Noh discloses diameters of the first G1 (Fig. 2, paragraph 0044) and second gate structures G2 (Fig. 2, paragraph 0044) are different from each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Gwon to form diameters of the first and second gate structures are different from each other, as taught by Noh, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 12, Gwon further discloses the semiconductor device of claim 11, wherein gate dielectric layers (145 and 245 in Fig. 2, paragraph 0053) of the first (120 in Fig. 2) and second gate structures (220 in Fig. 2) are in contact with a gate dielectric layer (135 and 235 in Fig. 2, paragraph 0117) of the third gate structure (130, 120_1, 220_1, and 230 in Fig. 2).
Regarding claim 13, Gwon further discloses the semiconductor device of claim 11, wherein the third gate structure (130, 120_1, 220_1, and 230 in Fig. 2) surrounds the first (120 in Fig. 2) and second gate structures (220 in Fig. 2) about a first axis and surrounds the nanostructured channel region 115 (Fig. 2) about a second axis different from the first axis.
Regarding claim 14, Gwon further discloses the semiconductor device of claim 11, wherein the first (120 in Fig. 2) and second gate structures (220 in Fig. 2) are separated (see Fig. 2, wherein 120 and 220 are separated by 115 of 120_1) from each other by a portion of the nanostructured channel region 115 (Fig. 2).
Regarding claim 15, Gwon further discloses the semiconductor device of claim 11, wherein the first (120 in Fig. 2) and second gate structures (220 in Fig. 2) are separated from each other by a portion of the third gate structure (130, 120_1, 220_1, and 230 in Fig. 2).
Regarding claim 16, Gwon further discloses the semiconductor device of claim 11, wherein the third gate structure (130, 120_1, 220_1, and 230 in Fig. 2) comprises a first gate portion (portions of 130, 120_1, 220_1, and 230 above 115 in Fig. 2) disposed on the nanostructured channel region 115 (Fig. 2) and a second gate portion (portions of 130, 120_1, 220_1, and 230 below 115 in Fig. 2) disposed between the nanostructured channel region 115 (Fig. 2) and the substrate 100 (Fig. 2), and wherein a bottom surface of the second gate portion (portions of 130, 120_1, 220_1, and 230 below 115 in Fig. 2) is on a same plane as bottom surfaces of the first (120 in Fig. 2) and second gate structures (220 in Fig. 2).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2018/0122703) (hereafter Cheng), in view of Frougier et al. (US 2021/0043727) (hereafter Frougier).
Regarding claim 17, Cheng discloses a method, comprising:
forming a first nanostructured layer (bottom 106 in Fig. 2A, paragraph 0047) on a substrate 102 (Fig. 2A, paragraph 0037);
forming a second nanostructured layer (top 106 in Fig. 2A, paragraph 0047) on the first nanostructured layer (bottom 106 in Fig. 2A);
forming a polysilicon structure 302 (Fig. 3A, paragraph 0039, wherein “polysilicon”) on the first nanostructured layer (bottom 106 in Fig. 2A);
replacing (see Figs. 3A and 15) the polysilicon structure 302 (Fig. 3A) with a masking layer (1502 and element number is not shown in Fig. 15 but see 304 in Fig. 8);
forming a first gate structure 1801b (Fig. 18, paragraph 0064) extending through the first (element number is not shown in Fig. 18 but see bottom 106 in Fig. 6) and second nanostructured layers (element number is not shown in Fig. 18 but see top 106 in Fig. 6) and the masking layer (1502 in Fig. 18); and
replacing (see Figs. 15 and 18) the masking layer (1502 and element number is not shown in Fig. 15 but see 304 in Fig. 8) with a second gate structure (1801a and 1801c in Fig. 18, paragraph 0064) surrounding the first gate structure (1801b in Fig. 18, paragraph 0064) and the second nanostructured layer (element number is not shown in Fig. 18 but see top 106 in Fig. 6).
Cheng does not disclose replacing the first nanostructured layer with a second gate structure.
Frougier discloses replacing (see Figs. 9 and 1A, wherein bottom 301 (Fig. 9) becomes bottom 111 (Fig. 1A), wherein the etched region of bottom 301 (Fig. 9) is replaced with 164 (Fig. 1A)) the first nanostructured layer (bottom 301 in Fig. 9) with a second gate structure (leftmost 164 and rightmost 164 in Fig. 1A, paragraph 0052).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng to include replacing the first nanostructured layer with a second gate structure, as taught by Frougier, since thinning (Frougier, paragraph 0010) the exposed center portions of the nanosheets within the gate opening to increase the separation distance between the nanosheets.
Regarding claim 18, Cheng further discloses the method of claim 17, wherein forming the first gate structure 1801b (Fig. 18) comprises forming a first gate opening (top portion of 1602 in Fig. 17, paragraph 0062) in the masking layer 1502 (Fig. 17), a second gate opening (bottom portion of 1602 in Fig. 17) in the first nanostructured layer (1702a in Fig. 17), and a third gate opening (portion of 1602 between 1702b and 1702c in Fig. 17) in the second nanostructured layer (1702c in Fig. 17).
Regarding claim 19, Cheng further discloses the method of claim 17, wherein replacing (see Figs. 15 and 18) the masking layer (1502 and element number is not shown in Fig. 15 but see 304 in Fig. 8) with the second gate structure (1801a and 1801c in Fig. 18) comprises: removing (see Fig. 16) the masking layer (element number is not shown in Fig. 16 but see 304 in Fig. 8) to expose top and bottom surfaces of the second nanostructured layer 1702c (Fig. 17).
Cheng does not disclose replacing the first nanostructured layer with the second gate structure comprises removing the first nanostructured layer to expose sidewalls of the second nanostructured layer, and oxidizing portions of the exposed sidewalls and top and bottom surfaces of the second nanostructured layer.
Frougier discloses replacing (see Figs. 9 and 1A, wherein bottom 301 (Fig. 9) becomes bottom 111 (Fig. 1A), wherein the etched region of bottom 301 (Fig. 9) is replaced with 164 (Fig. 1A)) the first nanostructured layer (bottom 301 in Fig. 9) with the second gate structure (leftmost 164 and rightmost 164 in Fig. 1A, paragraph 0052) comprises removing (see Fig. 15A and paragraph 0087, wherein “thinning process”) the first nanostructured layer (bottom 301 in Fig. 9) to expose sidewalls of the second nanostructured layer (top 111 in Fig. 15A), and oxidizing (see paragraph 0088, wherein “oxidize the exposed semiconductor surfaces of the first semiconductor material”) portions of the exposed sidewalls and top and bottom surfaces of the second nanostructured layer (top 301 in Fig. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng to include replacing the first nanostructured layer with the second gate structure comprises removing the first nanostructured layer to expose sidewalls of the second nanostructured layer, and oxidizing portions of the exposed sidewalls and top and bottom surfaces of the second nanostructured layer, as taught by Frougier, since thinning (Frougier, paragraph 0010) the exposed center portions of the nanosheets within the gate opening to increase the separation distance between the nanosheets.
Regarding claim 20, Cheng further discloses the method of claim 17, wherein replacing (see Figs. 15 and 18) the masking layer (1502 and element number is not shown in Fig. 15 but see 304 in Fig. 8) with the second gate structure (1801a and 1801c in Fig. 18) comprises:
removing (see Fig. 16) the masking layer (element number is not shown in Fig. 16 but see 304 in Fig. 8); and
performing a polishing process (“CMP” in paragraph 0068) to expose the top surface of the first gate structure 1801b (Fig. 18).
Cheng does not disclose replacing the first nanostructured layer with the second gate structure;
removing the first nanostructured layer to expose sidewalls of the first gate structure;
depositing a dielectric layer on a top surface and sidewalls of the first gate structure; and
depositing a conductive layer on the dielectric layer.
Frougier discloses replacing (see Figs. 9 and 1A, wherein bottom 301 (Fig. 9) becomes bottom 111 (Fig. 1A), wherein the etched region of bottom 301 (Fig. 9) is replaced with 164 (Fig. 1A)) the first nanostructured layer (bottom 301 in Fig. 9) with the second gate structure (leftmost 164 and rightmost 164 in Fig. 1A, paragraph 0052);
removing (see Figs. 9 and 15A) the first nanostructured layer (bottom 301 in Fig. 9) to expose sidewalls 165 (Fig. 15A) of the first gate structure (middle 164 in Fig. 1A);
depositing a dielectric layer (169 and 165 in Fig. 1A) on a top surface and sidewalls of the first gate structure (middle 164 in Fig. 1A); and
depositing a conductive layer 198 (Fig. 1A, paragraph 0068) on the dielectric layer (169 and 165 in Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cheng to include replacing the first nanostructured layer with the second gate structure; removing the first nanostructured layer to expose sidewalls of the first gate structure; depositing a dielectric layer on a top surface and sidewalls of the first gate structure; and depositing a conductive layer on the dielectric layer, as taught by Frougier, since thinning (Frougier, paragraph 0010) the exposed center portions of the nanosheets within the gate opening to increase the separation distance between the nanosheets.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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