DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 7-9, 12-14, 16, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu (PG Pub. No. US 2021/0327850 A1)
Regarding claim 1, Chiu teaches a semiconductor device (1), comprising:
a substrate (¶ 0022: 10);
a buffer layer (¶ 0024: 30) disposed on the substrate (fig. 1: 30 disposed on 10);
a channel layer (¶ 0024: 50) disposed on the buffer layer (fig. 1: 50 disposed on 30);
a barrier layer (¶ 0030: 60) disposed on the channel layer (fig. 1: 60 disposed on 50);
a first compound semiconductor layer (¶ 0021: 901 and/or 902) disposed on the barrier layer (fig. 1: 901/902 disposed on 60);
a second compound semiconductor layer (¶ 0021: 903) disposed on the first compound layer (fig. 1: 903 disposed on 901/902);
a gate metal (¶ 0021: gate conductor 904) disposed on the second compound semiconductor layer (fig. 1: 904 disposed on 903);
a first passivation layer (¶¶ 0021, 0041: first portion of composite layer 70) disposed on the first compound semiconductor layer, the second compound semiconductor layer and the gate metal (¶ 0040 & fig. 1: 70 disposed on 901/902, 903 and 903);
a second passivation layer (¶ 0041: second portion of composite layer 70) disposed on the first passivation layer (¶ 0042 & fig. 1: second portion of 70 disposed on first portion of 70);
source/drain electrodes (¶ 0021: 92/90) disposed on both sides of the gate metal (fig. 1: 92/90 disposed on sides of 904), and the source/drain electrodes penetrate through the second passivation layer, the first passivation layer, the first compound semiconductor layer, and the barrier layer (fig. 1: 92/90 penetrate through to channel layer 50).
Regarding claim 2, Chiu teaches the device as claimed in claim 1, wherein the first passivation layer comprises aluminum oxide, aluminum nitride, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof (¶ 0041: first portion of composite layer 70 includes AlN or Al2O3).
Regarding claim 4, Chiu teaches the device as claimed in claim 1, wherein the second passivation layer comprises aluminum oxide, hafnium oxide, aluminum nitride, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof (¶ 0041: second portion of composite layer 70 includes SiN or SiO2).
Regarding claim 7, Chiu teaches the device as claimed in claim 1, wherein the first compound semiconductor layer comprises undoped gallium nitride (¶ 0032: Chiu teaches 902 comprises gallium nitride based material, and is silent to 902 comprising dopant; therefore, the material of 902 meets the broadest reasonable interpretation of ‘undoped gallium nitride’).
Regarding claim 8, Chiu teaches the device as claimed in claim 1, wherein the second compound semiconductor layer comprises p-type gallium nitride (¶ 0033: 903 p-type comprises GaN).
Regarding claim 9, Chiu teaches the device as claimed in claim 1, wherein the metal gate comprises titanium nitride (¶ 0034: 904 comprises TiN).
Regarding claim 12, Chiu teaches a method of forming semiconductor device (¶ 0005, fig. 1: 1), comprising:
providing a substrate (¶ 0022: 10) wherein a buffer layer (¶ 0024: 30), a channel layer (¶ 0024: 50), and a barrier layer (¶ 0030: 60) are sequentially formed on the substrate (¶¶ 0024-0030 & fig. 3A: 30/50/60 sequentially formed on 10);
forming a first compound semiconductor layer (¶¶ 0031-0032, 0051: 901/901a and/or 902/902a) on the barrier layer (figs. 3A, 3D: 901/902 formed on 60);
forming a second compound semiconductor material layer (¶ 0051: 903a) on the first compound layer (figs. 3A, 3D: 903a formed on 901/901a and/or 902/902a);
etching the second compound semiconductor material layer to form a second compound semiconductor layer (¶ 0052: 903a etched to form 903);
forming a gate metal (¶¶ 0031, 0034: gate conductor 904) on the second compound semiconductor layer (fig. 1: 904 formed on 903);
forming a first passivation layer (¶¶ 0021, 0041: first portion of composite layer 70) on the first compound semiconductor layer, the second compound semiconductor layer and the gate metal (¶ 0040 & fig. 1: 70 formed on 901/902, 903 and 904);
forming a second passivation layer (¶ 0041: second portion of composite layer 70) on the first passivation layer (¶ 0042 & fig. 1: second portion of 70 formed on first portion of 70);
source/drain electrodes (¶ 0021: 92/90) disposed on both sides of the gate metal (fig. 1: 92/90 disposed on sides of 904), and the source/drain electrodes penetrate through the second passivation layer, the first passivation layer, the first compound semiconductor layer, and the barrier layer (fig. 1: 92/90 penetrate through to channel layer 50).
Regarding claim 13, Chiu teaches the method as claimed in claim 12, wherein the etching of the second compound semiconductor material layer stops at a surface of the first compound semiconductor layer (fig. 3C: etching 903 stops at surface of 902/902a).
Regarding claim 14, Chiu teaches the method as claimed in claim 12, wherein the first passivation layer is conformally formed on surfaces of the first compound semiconductor layer, the second compound semiconductor layer, and the gate metal (fig. 3E: first portion of 70 conformally formed on surfaces of 901/902, 903 and 904).
Regarding claim 16, Chiu teaches the method as claimed in claim 12, wherein the first passivation layer comprises aluminum oxide, aluminum nitride, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof (¶ 0041: first portion of composite layer 70 includes AlN or Al2O3).
Regarding claim 18, Chiu teaches the method as claimed in claim 12, wherein the second passivation layer is conformally formed on the first passivation layer (fig. 3E: second portion of 70 conformally formed on first portion of 70).
Regarding claim 20, Chiu teaches the method as claimed in claim 12, wherein the second passivation layer comprises aluminum oxide, hafnium oxide, aluminum nitride, silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof (¶ 0041: second portion of composite layer 70 includes SiN or SiO2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 5, 15, 17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu as applied to claims 1 and 12 above, and further in view of Chiu et al. (PG Pub. No. US 2016/0351684 A1, hereinafter referenced as ‘Chiu-684’).
Regarding claims 3 and 17, Chiu teaches the device as claimed in claim 1 and the method as claimed in claim 12, comprising a first passivation layer (first portion of 70).
Chiu does not teach wherein the first passivation layer has a thickness of 3 Å to 200 Å.
Chiu-684 teaches a device (¶ 0011 & fig. 1: 100) including forming a first passivation layer (¶ 0015: 122, including material similar to Chiu) with a thickness of 5 Å to 500 Å (¶ 0015: 122 has a thickness of between approximately 5 angstroms and approximately 500 angstroms).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first passivation layer of Chiu with the thickness of Chiu-684, as a means to provide a high quality film, avoid thermal budget issues, and provide good step coverage (Chiu-684, ¶ 0015).
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed range of 3 Å to 200 Å overlaps the range disclosed by Chiu-684 (approximately 5 angstroms and approximately 500 angstroms).
Regarding claims 5 and 21, Chiu teaches the device as claimed in claim 1 and the method as claimed in claim 12, comprising a second passivation layer (second portion of 70).
Chiu does not teach wherein the second passivation layer has a thickness of 100 Å to 2000 Å.
Chiu-684 teaches a device (¶ 0011 & fig. 1: 100) including forming a second passivation layer (¶ 0016: 124, including material similar to Chiu) with a thickness of about 500 Å (¶ 0016: 124 has a thickness ranging from approximately 50 nanometers).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the second passivation layer of Chiu, as a means to help protect the first passivation layer during processing (Chiu-684, ¶ 0016).
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, the general condition of second passivation layer thickness is disclosed by Chiu-684 (second passivation layer of approximately 50 nanometers, minimizing thermal budget), such that discovering the claimed range of 100 Å to 2000 Å would involve only routine skill.
Regarding claim 15, Chiu teaches the method as claimed in claim 12, comprising formation of a first passivation layer (first portion of 70).
Chiu further teach wherein the first passivation layer comprises aluminum oxide or aluminum nitride, or a combination thereof (¶ 0041: first portion of composite layer 70 includes AlN or Al2O3).
Chiu is silent to wherein the formation of the first passivation layer is performed at 400°C or below.
Chiu-684 teaches a device (¶ 0011 & fig. 1: 100) including forming a first passivation layer (¶ 0015: 122, including material similar to Chiu) wherein the formation of the first passivation layer is performed at 500°C or below (¶ 0015: 122 formed at a temperature between 200° C. and 500° C).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first passivation layer formation of Chiu with the temperature of Chiu-684, as a means to provide a high quality film, avoid thermal budget issues, and provide good step coverage (Chiu-684, ¶ 0015).
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, the general condition of second passivation layer temperature is disclosed by Chiu-684 (¶ 0015), such that discovering the claimed range of 400 °C or below would involve only routine skill.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chiu as applied to claim 12, and further in view of Chu et al. (Patent No. US 9,761,438 B1).
Regarding claim 19, Chiu teaches the method as claimed in claim 12, comprising formation of the second passivation layer (second portion of 70).
Chiu further teach wherein the second passivation layer comprises silicon oxide or silicon nitride, or a combination thereof (¶ 0041: second portion of composite layer 70 includes SiN or SiO2).
Chiu is silent to wherein the formation of the second passivation layer is performed at 350°C or above.
Chu teaches forming passivation layers including material such as SiN or SiO2 above a temperature of 350°C (col. 5 lines 1-18: PECVD deposited SiN passivation layers 12 and/or 20 are deposited at a temperature of about 400 degree C or above).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to form the second passivation layer of Chiu above a temperature of 350°C, as a means to optimize adhesion (Chu, col. 1 lines 24-25).
Claims 10-11 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu as applied to claims 1 and 12, and further in view of You et al. (PG Pub. No. US 2023/0369424 A1).
Regarding claim 10, Chiu teaches the device as claimed in claim 1, further comprising:
a third passivation layer (¶ 0042: 80), disposed on the first passivation layer and the second passivation layer (fig. 1: 80 disposed on first and second portions of 70).
Chiu does not teach the third passivation layer is in direct contact with the first passivation layer on one side of the metal gate.
You teaches a device (¶ 0092 & fig. 7: 200B) including a third passivation layer (¶ 0077: 250), disposed on a first passivation layer (220), a second passivation layer (230) and a metal gate (¶¶ 0035, 0083 & fig. 7: 250 disposed on 220, 230 and metal gate electrode 214), wherein the third passivation layer is in direct contact with the first passivation layer on one side of the metal gate (fig. 7: 250 in direct contact with 220 on at least one side of 214).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the passivation layers of Chiu with the arrangement of You, as a means to collectively make the electric field distribution in the semiconductor device uniform, reduce parasitic capacitances and resistance of a 2DEG region, enhancing electrical properties of the semiconductor device (You, ¶ 0010).
Regarding claim 11, Chiu in view of You teaches the device as claimed in claim 10, wherein the third passivation layer comprises aluminum oxide, aluminum nitride, silicon oxide, silicon oxynitride, silicon nitride, gallium nitride, or a combination thereof (Chiu, ¶ 0042).
Regarding claim 22, Chiu teaches the method as claimed in claim 12, further comprising:
performing a patterning process on the second passivation layer to expose a part of the surface of the first passivation layer on one side of the gate metal (¶ 0056: patterning process performed on second portion of 70 to expose a first portion of 70); and
forming a third passivation layer on the second passivation layer and the first passivation layer (¶ 0057 & fig. 3G: 80 formed on second/upper and first/lower portions of 70).
Chiu does not teach wherein the third passivation layer is in direct contact with the first passivation layer on the one side of the metal gate.
You teaches a method of forming a device (¶ 0092 & fig. 7: 200B) including a third passivation layer (¶ 0077: 250), disposed on a first passivation layer (220), a second passivation layer (230) and a metal gate (¶¶ 0035, 0083 & fig. 7: 250 disposed on 220, 230 and metal gate electrode 214), the method including:
performing a patterning process on the second passivation layer to expose a part of the surface of the first passivation layer on one side of the gate metal (¶ 0090 & fig. 6C: patterning process performed on 230 to expose a first portion of 220 on at least one side of 214); and
forming a third passivation layer on the second passivation layer and the first passivation layer (¶ 0091 & fig. 7: 250 formed on 230 and 220),
wherein the third passivation layer is in direct contact with the first passivation layer on one side of the metal gate (fig. 7: 250 in direct contact with top surface of 220 on at least one side of 214).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the passivation layers of Chiu with the arrangement of You, as a means to collectively make the electric field distribution in the semiconductor device uniform, reduce parasitic capacitances and resistance of a 2DEG region, enhancing electrical properties of the semiconductor device (You, ¶ 0010).
Response to Arguments
Applicant’s arguments, see page, filed 8/24/2026, with respect to the formal objection to the specification have been fully considered and are persuasive, Accordingly, the formal objection to the specification has been withdrawn.
Applicant's arguments with respect to the 35 USC 102 and 35 USC 103 rejections of claims 1-23 have been fully considered but they are not persuasive for the following reasons.
Regarding the Applicant’s argument stating:
“However, as shown in FIG. 1 (reproduced below) of Chiu, the alleged source/drain electrodes 92/90 only penetrate through the alleged first/second passivation layer 70 and the alleged barrier layer 60, without penetrating the alleged first compound semiconductor layer 901/902” (emphasis added),
the Examiner respectfully disagrees. As shown in figs. 1 and 3C-3F of Chiu, an opening penetrating compound semiconductor layer 901/902 is formed to expose a surface of barrier layer 60, and source/drain electrodes 92/90 are subsequently formed in the opening and extending through barrier layer 60. As such, source/drain electrodes 92/90 at least indirectly penetrate 901/902 by way of the patterned opening.
The Applicant’s arguments are not persuasive, and the rejections of claims 1 and 12 are maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lee et al. (US 2014/0252368 A1) teaches a semiconductor device (fig. 4), including source/drain electrodes (182, 184) disposed on both sides of a gate metal (186), the source/drain electrodes penetrating through a second passivation layer (176), a first passivation layer (174), a first compound semiconductor layer (150), and a barrier layer (164).
Chang et al. (US 2022/0045203 A1) teaches a semiconductor device (fig. 8), including source/drain electrodes (110, 112) disposed on both sides of a gate metal (114), the source/drain electrodes penetrating through a passivation layer (138), a first compound semiconductor layer (128), and a barrier layer (126).
Akutsu (US 2021/0376136 A1) teaches a semiconductor device (fig. 1), including source/drain electrodes (11, 12) disposed on both sides of a gate metal (22), the source/drain electrodes penetrating through a second passivation layer (8), a first passivation layer (7), a first compound semiconductor layer (6), and a barrier layer (5).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
