DETAILED ACTION
This correspondence is in response to the communications received May 1, 2024. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant has made no claim to the benefit of an earlier filing date.
Relevant Prior Art
Ecton et al. (US 2025/0309015) Fig. 4B, shown below.
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Shan et al. (US 2025/0218880) Fig. 1, shown below
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Pietambaram et al. (2023/0197697) Fig. 2, shown below.
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Acikalin et al. (US 2025/0298202) Fig. 3, shown below.
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Kong et al. (US 2025/0300062) Fig. 1, shown below.
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Ecton et al. (US 2025/0300086) Fig. 1, shown below.
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May et al. (US 2025/0293122) Fig. 1, shown below. ¶ 0041, “support structure 155 may include a glass material”.
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Pietambaram et al. (US 2025/0266340) Fig. 1, shown below.
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Ecton et al. (US 2025/0266395) Fig. 8, shown below. ¶ 0054, “Substrate 700 illustrates a layer of glass 702/802/902/1002”.
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Chen et al. (US 2025/0266343) Fig. 15, shown below.
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Yong et al. (US 2025/0226331) Fig. 10, shown below.
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Liu et al. (US 2025/0218926) Fig. 1B, shown below.
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Marin et al. (US 2025/0210469) Fig. 4K, shown below.
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Ecton et al. (US 2025/0096143) Fig. 1, shown below.
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Yim et al. (US 2024/0395720) Fig. 1, shown below.
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Marin et al. (US 2024/0079337) Fig. 1, shown below.
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Ecton et al. (US 12,635,541) Fig. 3, shown below.
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Darmawikarta et al. (US 2023/0197661) Fig. 1, shown below.
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Darmawikarta et al. (US 2022/0375882) Fig. 1A, shown below.
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Ganesan et al. (US 2021/0193579 or US 12,261,124) Fig. 1, shown below. Layer 12 is glass, “Substrate 12 includes embedded components of a semiconductor material (e.g., a silicon, gallium, indium, germanium, or variations or combinations thereof) and one or more insulating layers, such as organic based build up film, glass-reinforced epoxy, such as FR-4, polytetrafluorethylene (Teflon), cotton-paper reinforced epoxy (CEM-3), phenolic-glass (G3), paper-phenolic (FR-1 or FR-2), polyester-glass (CEM-5), or any other dielectric layer, that can be used in printed circuit boards (PCBs).”, ¶ 0011.
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 2D and 3G, a package structure, comprising:
a core substrate (“core layer 200”, ¶ 0026),
a build up structure (300a, 300b) disposed on the core substrate (on 200),
wherein the build up structure (upper 300a) includes a recess (310) in the build up structure (3110 in 300a);
a semiconductor die (one of 600a, 600b, ¶ 0052), disposed on the build up structure (on 300a) and over the core substrate (over 200);
a bridge die (100b, ¶ 0044), disposed in the recess (310, ¶ 0044) of the build up structure (300a) and between the semiconductor die (one of 600b, 600a) and the core substrate (200),
wherein the bridge die (100b) includes first connectors (120, ¶ 0037) and second connectors (122, ¶ 0037) respectively disposed on two opposing surfaces of the bridge die (top and bottom of 100b, which is analogous to10a in Fig. 2D) and conductive through vias (104, ¶ 0037) penetrating the bridge die (102 itself is the actual semiconductor substrate, that is the basis for 100b/10a) and electrically connected with the first and second connectors (TSV 104 electrically connect to 120/122), and the bridge die (100b) is electrically connected with the semiconductor die (one of 600a, 600b) and the core substrate (200) respectively through the first connectors and second connectors (120, 122).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. (US 2025/0210426) in view of Song (US 2024/0071943).
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Regarding claim 1, the prior art of Shan discloses in Figs. 1, a package structure (¶ 0034 discusses Fig. 1 showing an assembly based on a package substrate, however Shan does not explicitly use the term, “package substrate”), comprising:
a core substrate (¶ 0038, “glass core 110”),
a build up structure (element 112A, “dielectric material 112 (e.g., a first dielectric material layer 112A”, ¶ 0031, and “112 may include an organic material, such as an organic build-up film.”, ¶ 0035) disposed on the core substrate (112A on 110),
wherein the build up structure (112A) includes a recess (“cavity 119”, ¶ 0031) in the build up structure (119 in 112A);
a semiconductor die (114-2, 114-3, “dies 114” may be used to refer to a collection of dies 114-1, 114-2, and so on, etc”, ¶ 0026, where semiconductor die disclosed in ¶ 0033, “a die 114 may include a semiconductor material”), disposed on the build up structure (114-1 and 114-2 on 112A) and over the core substrate (114-1, 114-2 are both on 112A);
a bridge die (“double-sided bridge die 114-1”, ¶ 0031), disposed in the recess of the build up structure (114-1 in 119) and between the semiconductor die and the core substrate (114-1 is between 114-2, 114-3 and 110),
wherein the bridge die (114-1) includes first connectors (“first conductive contacts 122”, ¶ 0031) and second connectors (“second conductive contacts 124”, ¶ 0031) respectively disposed on two opposing surfaces of the bridge die (122, 124 are on either side of 114-1) and conductive through vias (“through-silicon vias (TSVs) 125”, ¶ 0031) penetrating the bridge die (125 penetrating 114-1) and electrically connected with the first and second connectors (125 connect 122 to 124), and
the bridge die (114-1) is electrically connected with the semiconductor die (114-2, 114-3) and the core substrate (110) respectively through the first connectors and second connectors (connectors 122, 124 connect 114-1 to 114-2, 114-3 and to 110, through further connectors “conductive trace 108A”, ¶ 0031, “conductive contacts 121”, ¶ 0037, “interconnects 130”, ¶ 0031).
Shan does not explicitly teach that the package configuration is a “package substrate”.
Song teaches in ¶ 0004, “To solve miniaturization and cost reduction demands, a semiconductor package using embedded multi-die interconnect bridge (EMIB) architectures provides high-density interconnects between heterogeneous dies on a single package by embedding a bridge (e.g., a silicon bridge) in a package substrate.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of the package configuration is a “package substrate”, as disclosed by Song in the system of Shan, for the purpose of including all features of active IC dies, bridge dies, build up layers and substrate into an inclusive whole known as a package substrate. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Shan et al. disclose the package structure according to claim 1, wherein the core substrate includes a glass core layer (¶ 0038, “glass core 110”), and through glass vias (“TGVs 115”, ¶ 0039) penetrating through the core substrate (“a glass core 110 with TGVs 115”, ¶ 0039).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. (US 2025/0210426) in view of Song (US 2024/0071943) in view of Shan et al. (US 2024/0213170, hereinafter referred to as “Shan ‘170”) in view of Wang et al. (US 2023/0189205).
Regarding claim 4, the prior art of Shan et al. disclose the package structure according to claim 3, however Shan does not discloses, “wherein the electronic component includes a semiconductor substrate and through semiconductor vias.”
Wang discloses in Fig. 1, wherein the electronic component (130) includes a semiconductor substrate and through semiconductor vias (“The dual-sided interconnect die 130 may be an active die. That is, the dual-sided interconnect die 130 may include one or more transistors, processors, logic, or some other “active” element that is capable of performing some type of logic or processing. The dual-sided interconnect die 130 may further include one or more plated vias such as plated vias 160.”, ¶ 0042, where it is understood that a die with transistors would inherently be made of semiconductor material).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “wherein the electronic component includes a semiconductor substrate and through semiconductor vias”, as disclosed by Wang in the system of Shan, for the purpose of increasing functionality and electrical connection flexibility for the overall package arrangement. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 3, 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. (US 2025/0210426) in view of Song (US 2024/0071943) in view of Shan et al. (US 2024/0213170, hereinafter referred to as “Shan ‘170”).
Regarding claim 3, the prior art of Shan et al. disclose the package structure according to claim 2, however Shan does not disclose, “further comprising an electronic component disposed in a cavity of the glass core layer of the core substrate, wherein the electronic component is electrically connected with the bridge die through the second connectors and the build up structure.”
Shan ‘170 discloses in Figs. 1-2H and 5, further comprising an electronic component (“active component die 108”, ¶ 0017) disposed in a cavity (“cavities 106”, ¶ 0017) of the glass core layer (“glass core layer 104”, ¶ 0017) of the core substrate (portion of 102 level with 104), wherein the electronic component (108) is electrically connected with the bridge die (equivalent being 122 MIB, discussed in ¶ 0019) through the second connectors and the build up structure (“The MIB 122 can provide electrical continuity between at least one input/output (I/O) pad of the active component die 108 disposed in the cavity 106”, ¶ 0019, conductors shown below and above 122, first and second connectors already disclosed in the rejection of claim 1.).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “further comprising an electronic component disposed in a cavity of the glass core layer of the core substrate, wherein the electronic component is electrically connected with the bridge die through the second connectors and the build up structure”, as disclosed by Shan ‘170 in the system of Shan, for the purpose of increasing functionality of the overall package arrangement. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 5, the prior art of Shan et al. disclose the package structure according to claim 3, and Shan ‘170 discloses in Figs. 1-2H and 5, wherein the semiconductor die (equivalent being “active component dies 534”, ¶ 0033) is electrically connected with the electronic component (108) through the bridge die (by way of 522), the build up structure (510) and the core substrate (504).
Regarding claim 6, the prior art of Shan et al. disclose the package structure according to claim 3, and Shan ‘170 discloses in Figs. 1-2H and 5, further comprising another electronic component (the second of the two 108) embedded in the core substrate (in 104/504), wherein the another electronic component (second 108) is electrically connected with the semiconductor die (equivalent being the second 534) through the core substrate (104/504) and the build up structure (510).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. (US 2025/0210426) in view of Song (US 2024/0071943) in view of Alam et al. (US 2025/0167192).
Regarding claim 7, the prior art of Shan et al. disclose the package structure according to claim 1, and Shan discloses, further comprising another semiconductor die (114-3) disposed on the build up structure (on 112A) over the core substrate (over 110) and beside the semiconductor die (114-3 is next to 114-2), wherein the another semiconductor die (114-3) is electrically connected with the semiconductor die (114-2) through the bridge die (114-1).
Although the “bridge die 114-1” is understood to likely connect 114-2 to 114-3, Shan does not explicitly state this feature.
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Alam discloses in Figs. 1 and 3A, wherein the another semiconductor die is electrically connected with the semiconductor die through the bridge die (“two IC dice 124 in an upper tier communicate with each other via the bridge die 106”, ¶ 0022).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “wherein the another semiconductor die is electrically connected with the semiconductor die through the bridge die”, as disclosed by Alam in the system of Shan, for the purpose of increasing functionality by allowing cooperation between the two semiconductor dies. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 8 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. (US 2025/0210426) in view of Song (US 2024/0071943) in view of Shan et al. (US 2024/0213170, hereinafter referred to as “Shan ‘170”) in view of Saber (US 2025/0112144) in view of Alam et al. (US 2025/0167192).
Regarding claim 8, the prior art of Shan discloses in Figs. 1, a package structure (¶ 0034 discusses Fig. 1 showing an assembly based on a package substrate, however Shan does not explicitly use the term, “package substrate”), comprising:
a substrate (110) comprising a glass core layer (¶ 0038, “glass core 110”),
a first build up structure (element 112A, “dielectric material 112 (e.g., a first dielectric material layer 112A”, ¶ 0031, and “112 may include an organic material, such as an organic build-up film.”, ¶ 0035) and a second build up structure (similar to 112A, “further layers 111”, ¶ 0039, which is built up layer by layer from core 110. The “build up” aspect will be addressed below.) disposed on an upper surface and a lower surface of the substrate respectively (112A on top surface of 110, and 111 on lower surface of 110);
a bridge die (“double-sided bridge die 114-1”, ¶ 0031) embedded in the first build up structure (114-1 embedded in 119 in 112A);
a first semiconductor die (114-2, 114-3, “dies 114” may be used to refer to a collection of dies 114-1, 114-2, and so on, etc”, ¶ 0026, where semiconductor die disclosed in ¶ 0033, “a die 114 may include a semiconductor material”) and a second semiconductor die (114-3) disposed over the bridge die (over 114-1) and disposed on the first build up structure (114-2, 114-3 on 112A).
First, Shan does not explicitly teach that the package configuration is a “package substrate”.
Song teaches in ¶ 0004, “To solve miniaturization and cost reduction demands, a semiconductor package using embedded multi-die interconnect bridge (EMIB) architectures provides high-density interconnects between heterogeneous dies on a single package by embedding a bridge (e.g., a silicon bridge) in a package substrate.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of the package configuration is a “package substrate”, as disclosed by Song in the system of Shan, for the purpose of including all features of active IC dies, bridge dies, build up layers and substrate into an inclusive whole known as a package substrate. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Shan does not disclose,
“wherein the glass core layer includes a cavity extending through the glass core layer,
an electronic component embedded within the cavity of the glass core layer,
wherein the electronic component is electrically connected to the first and the second semiconductor dies through the bridge die.”
Shan ‘170 discloses in Fig. 1-2H and 5, wherein the glass core layer (“glass core layer 104”, ¶ 0018, which is analogous to 514) includes a cavity (“cavities 106”, ¶ 0017) extending through the glass core layer (106 extends through 104/504, as can be seen in Fig. 2C),
an electronic component (“at least one active component die 108 is disposed in each of the cavities 106”, ¶ 0017) embedded within the cavity (in 106) of the glass core layer (of 104/504),
wherein the electronic component (108) is electrically connected to the first and the second semiconductor dies (two “active component die 544”, ¶ 0036) through the bridge die (“The MIB 522 can provide interconnection for the glass core layer active component dies 508 and mold layer active component dies 544.”, ¶ 0039).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the glass core layer includes a cavity extending through the glass core layer,
an electronic component embedded within the cavity of the glass core layer,
wherein the electronic component is electrically connected to the first and the second semiconductor dies through the bridge die”, as disclosed by Shan ‘170 in the system of Shan, for the purpose allowing for accommodating further electronic devices which can increase the overall package functionality with memory function, processing function, etc. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Third, Shan does not explicitly call the 111 a “build up structure”.
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The prior art of Saber discloses in Fig. 7A, and in ¶ 0084, a second build up structure (both upper 109-2 and lower 109-1 wiring regions are called “build-up” layers, “The layer of conventional dielectric material 109 may include bismaleimide triazine (BT) resin, polyimide materials, epoxy materials (e.g., glass reinforced epoxy matrix materials, epoxy build-up films, or the like)”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “a second build up structure”, as disclosed by Saber in the system of Shan, for the purpose of allowing for complex routing electrical connections to allow for electrical connection between dissimilar electrical components. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Fourth, Shan does not explicitly disclose, “wherein the first semiconductor die is electrically connected with the second semiconductor die through the bridge die”.
The prior art of Alam discloses in Figs. 1, 2A and 3A, wherein the first semiconductor die (“two IC dice 124”, ¶ 0022, where dice is understood to mean semiconductor dice, and this limitation is previously disclosed by Shan) is electrically connected with the second semiconductor die through the bridge die (“two IC dice 124 in an upper tier communicate with each other via the bridge die 106”, ¶ 0022).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “wherein the first semiconductor die is electrically connected with the second semiconductor die through the bridge die”, as disclosed by Alam in the system of Shan, for the purpose of increasing functionality by allowing cooperation between the two semiconductor dies. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 10, the prior art of Shan et al. disclose the package structure according to claim 8, and Wang discloses in Fig. 1, wherein the substrate (“glass dielectric 120”, ¶ 0044) includes a through glass via (“TGVs 135”, ¶ 0044) extending from the upper surface to the lower surface of the substrate and penetrating through the glass core layer (135 extends from top to bottom of 120 and goes through 120).
Regarding claim 11, the prior art of Shan et al. disclose the package structure according to claim 10, and Wang discloses, wherein the through glass via comprises a plated through hole structure (“copper may be electroplated within the TGV 135 120 to form a copper pillar.”, ¶ 0044), and the through glass via (135) is electrically connected with the first and the second build up structures (135 connects to either side of glass substrate, where build up structures are located).
Regarding claim 12, the prior art of Shan et al. disclose the package structure according to claim 8, and Shan discloses, wherein the bridge die comprises:
a semiconductor substrate (““dies 114” may be used to refer to a collection of dies 114-1, 114-2, and so on, etc”, ¶ 0026, where semiconductor die disclosed in ¶ 0033, “a die 114 may include a semiconductor material”);
first connectors (“conductive contacts 122”, ¶ 0031) disposed on a first side of the semiconductor substrate (bottom surface of 114-1);
through substrate vias (TSVs) (“through-silicon vias (TSVs) 125”, ¶ 0031) extending through the semiconductor substrate (through 114-1) and electrically connected with the first connectors (125 directly connected to 122);
a redistribution structure (112B, and 121) disposed on a second side of the semiconductor substrate (on top surface of 114-1) opposing the first side (top versus bottom of 114-1) and electrically connected to the TSVs (“conductive contacts 121”, ¶ 0037, connects to 125 by way of “conductive contacts 124”, ¶ 0031); and
second connectors (“interconnects 130”, ¶ 0031) disposed on the redistribution structure (130 on 121),
wherein the second connectors (130) and the semiconductor substrate (114-1) are respectively located on opposite sides of the redistribution structure (130 is on opposite side of 121 from 114-1).
Shan does not explicitly describe 112B/121 in Fig. 1, a “build up structure”, however as is commonly known in the art, this is what a build up structure is in essence.
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The prior art of Saber discloses in Fig. 7A, and in ¶ 0084, a build up structure (both upper 109-2 and lower 109-1 wiring regions are called “build-up” layers, “The layer of conventional dielectric material 109 may include bismaleimide triazine (BT) resin, polyimide materials, epoxy materials (e.g., glass reinforced epoxy matrix materials, epoxy build-up films, or the like)”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “a second build up structure”, as disclosed by Saber in the system of Shan, for the purpose of allowing for complex routing electrical connections to allow for electrical connection between dissimilar electrical components. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 13, the prior art of Shan et al. disclose the package structure according to claim 12, and Shan et al. disclose, wherein the first and second build up structures (112A and 111 of Shan in Fig. 1, which is combined with Saber to teach the term “build up” in the rejection of claim 8, as previously addressed.) include electrically interconnected metal layers (“conductive trace 108A”, ¶ 0031) sandwiched between insulating layers (“dielectric material 112 (e.g., a first dielectric material layer 112A and a second dielectric material layer 112B, as shown, together referred to as “one or more layers of the dielectric material 112”)”, ¶ 0031, and 111 being further shown to be build up layers by Saber, see Saber describing these layers in ¶ 0084, “dielectric material 109-1”).
Regarding claim 14, the prior art of Shan et al. disclose the package structure according to claim 13, wherein the bridge die (114-1) is electrically connected with the first and second semiconductor dies (Shan’s 114-2, 114-3 electrically connect to 114-1 as shown in Fig. 1) through the second connectors (top connections of 114-1, already described above) and electrically connected with the electronic component through the first connectors and the metal layers of the first build up structure (Shan already has shown the lower connectors of 114-1, then the combination rejection in view of Shan ‘170 is used to teach the electrical connection of “MIB 522 that can electrically connect the glass core layer active component dies 508 together, the mold layer active component dies 544 together,”, ¶ 0037, where the build up wiring of the substrate intervenes as shown in Fig. 5, so they too are in the electrical pathway connecting the chip connections described in ¶ 0037.).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. (US 2025/0210426) in view of Song (US 2024/0071943) in view of Shan et al. (US 2024/0213170, hereinafter referred to as “Shan ‘170”) in view of Saber (US 2025/0112144) in view of Alam et al. (US 2025/0167192) in view of Wang et al. (US 2023/0187205).
Regarding claim 9, the prior art of Shan et al. disclose the package structure according to claim 8, however Shan does not disclose, “wherein a thickness of the glass core layer is greater than a thickness of the electronic component.”
Wang discloses in Fig. 1, wherein a thickness of the glass core layer (“glass dielectric 120”, ¶ 0031) is greater than a thickness of the electronic component (120 thicker than 130, “die 130”, ¶ 0031. Although it is not stated that the components are drawn to scale, the relationship of thicknesses can still be gleaned from the drawing as shown in Fig. 1, where 120 is thicker than 130.)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “wherein a thickness of the glass core layer is greater than a thickness of the electronic component”, as disclosed by Wang in the system of Shan, for the purpose of protecting the electronic component during the fabrication of the build up layers on the glass core substrate. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. (US 2025/0210426) in view of Song (US 2024/0071943) in view of Shan et al. (US 2024/0213170, hereinafter referred to as “Shan ‘170”) in view of Saber (US 2025/0112144) in view of Alam et al. (US 2025/0167192) in view of Soetan-Dodd et al. (US 2024/0332195, hereinafter referred to as ‘SD’).
Regarding claim 15, the prior art of Shan et al. disclose the package structure according to claim 8, however Shan does not disclose, “further comprising solder resist layers disposed on outermost surfaces of the first and second build up structures, and conductive terminals disposed on the solder resist layers, wherein the conductive terminals on the first and the second build up structure are electrically connected with the first and second semiconductor dies and electrically connected with the electronic component.”
SD discloses in Fig. 1, further comprising solder resist layers (“Solder resist layers 103”, ¶ 0020) disposed on outermost surfaces of the first and second build up structures (The build up structures have already been shown in the rejections above in this chain of dependency, here the analogous placeholder of a substrate is element 101 with equivalent build up layers 102/117/115), and conductive terminals disposed on the solder resist layers (104/151, ¶ 0020), wherein the conductive terminals on the first and the second build up structure are electrically connected with the first and second semiconductor dies and electrically connected with the electronic component (151/104 are in an electrical pathway connecting to both of equivalent semiconductor dies 150, ¶ 0020).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “further comprising solder resist layers disposed on outermost surfaces of the first and second build up structures, and conductive terminals disposed on the solder resist layers, wherein the conductive terminals on the first and the second build up structure are electrically connected with the first and second semiconductor dies and electrically connected with the electronic component”, as disclosed by SD in the system of Shan, for the purpose of providing insulation to the build up pads to prevent shorting while connection of the solder joints and insulate between the solder joints after formation. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 16, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. (US 2025/0210426) in view of Song (US 2024/0071943) in view of Shan et al. (US 2024/0213170, hereinafter referred to as “Shan ‘170”) in view of Saber (US 2025/0112144).
Regarding claim 16, the prior art of Shan discloses in Figs. 1, a method of manufacturing a package structure (¶ 0034 discusses Fig. 1 showing an assembly based on a package substrate, however Shan does not explicitly use the term, “package substrate”, which will be addressed subsequently below), comprising:
providing a substrate (110) including a glass core layer (¶ 0038, “glass core 110”);
forming a first build up structure (insulators “dielectric material layer 112A”, ¶ 0031 and conductors “conductive material 108B”, ¶ 0031. Build up aspect will be addressed below.) and a second build up structure (insulators and conductors in “further layers 111”, ¶ 0039, which are not further elaborated upon, however in comparison to 112A/108B which are described, one can see that conductors and insulators are present. However, this will be further disclosed in the combination rejection below.) on an upper surface (112A, 108B on top surface of 110) and a lower surface (111 on lower surface of 110) opposite to the upper surface of the substrate (top and lower surfaces of 110 oppose each other);
embedding a bridge die (“double-sided bridge die 114-1”, ¶ 0031) in the first build up structure (114-1 in 112A/108B),
wherein the bridge die (114-1) is electrically connected to the core layer (110) through the first build up structure (108B) formed on the upper surface of the core layer (formed on top surface of 110); and
providing and bonding a first semiconductor die (first semiconductor die interpreted as 114-2, and second semiconductor die interpreted as 114-3, “dies 114” may be used to refer to a collection of dies 114-1, 114-2, and so on, etc”, ¶ 0026, where semiconductor die disclosed in ¶ 0033, “a die 114 may include a semiconductor material”) and a second semiconductor die (114-3) onto the first build up structure (on 112A, 108B).
First, Shan does not explicitly teach that the package configuration is a “package substrate”.
Song teaches in ¶ 0004, “To solve miniaturization and cost reduction demands, a semiconductor package using embedded multi-die interconnect bridge (EMIB) architectures provides high-density interconnects between heterogeneous dies on a single package by embedding a bridge (e.g., a silicon bridge) in a package substrate.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of the package configuration is a “package substrate”, as disclosed by Song in the system of Shan, for the purpose of including all features of active IC dies, bridge dies, build up layers and substrate into an inclusive whole known as a package substrate. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Shan does not disclose,
“providing a substrate including a glass core layer with a cavity extending through the glass core layer;
embedding an electronic component in the cavity of the glass core layer;
wherein the electronic component is electrically connected to the first and the second semiconductor dies through the bridge die.”
Shan ‘170 discloses in Fig. 1-2H and 5, providing a substrate including a glass core layer (“glass core layer 104”, ¶ 0018, which is analogous to 514) with a cavity (“cavities 106”, ¶ 0017) extending through the glass core layer (106 extends through 104/504, as can be seen in Fig. 2C);
embedding an electronic component (“at least one active component die 108 is disposed in each of the cavities 106”, ¶ 0017) in the cavity (in 106) of the glass core layer (104/504);
wherein the electronic component (108) is electrically connected to the first and the second semiconductor dies (two “active component die 544”, ¶ 0036) through the bridge die (“The MIB 522 can provide interconnection for the glass core layer active component dies 508 and mold layer active component dies 544.”, ¶ 0039).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“providing a substrate including a glass core layer with a cavity extending through the glass core layer;
embedding an electronic component in the cavity of the glass core layer;
wherein the electronic component is electrically connected to the first and the second semiconductor dies through the bridge die.”, as disclosed by Shan ‘170 in the system of Shan, for the purpose allowing for accommodating further electronic devices which can increase the overall package functionality with memory function, processing function, etc. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Third, Shan does not explicitly call the 111 a “build up structure”.
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The prior art of Saber discloses in Fig. 7A, and in ¶ 0084, a second build up structure (both upper 109-2 and lower 109-1 wiring regions are called “build-up” layers, “The layer of conventional dielectric material 109 may include bismaleimide triazine (BT) resin, polyimide materials, epoxy materials (e.g., glass reinforced epoxy matrix materials, epoxy build-up films, or the like)”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “a second build up structure”, as disclosed by Saber in the system of Shan, for the purpose of allowing for complex routing electrical connections to allow for electrical connection between dissimilar electrical components. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 17, the prior art of Shan et al. disclose the method according to claim 16, and Shan ‘170 discloses in Figs. 1-2H and 5,
wherein embedding the electronic component (108/508) in the glass core layer (104/504) comprises:
patterning the glass core layer to form the cavity in the glass core layer (this step can be seen in the progression from Fig. 2A to 2B, where a cavity 106 is formed in 104);
disposing the electronic component in the cavity (this step can be seen in the progression from Fig. 2C to 2D, where 108/508 is placed into cavity 106); and
applying an insulating material layer onto the glass core layer to encapsulate the electronic component and fully cover the glass core layer (build up layers 110 and 112, ¶ 0018 added to 104, in Fig. 2D, then further build up layers as shown in Fig. 2E including metal layers 114, ¶ 0018 and visible insulators separating the plural 114, to fully encapsulated by step of Fig. 5, where build up layer 510 and 512 fully encapsulate 508, ¶ 0035).
Regarding claim 18, the prior art of Shan et al. disclose the method according to claim 17, and Shan discloses in Fig. 1, further comprising forming a through glass via (“TGVs 115”, ¶ 0039) extending from the upper surface to the lower surface of the substrate (115 extend from top to bottom surface of 110) and penetrating through the glass core layer (115 penetrate through 110).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. (US 2025/0210426) in view of Song (US 2024/0071943) in view of Shan et al. (US 2024/0213170, hereinafter referred to as “Shan ‘170”) in view of Saber (US 2025/0112144) in view of Wang et al. (US 2023/0187205).
Regarding claim 19, the prior art of Shan et al. disclose the method according to claim 18, and Shan does not disclose, “wherein forming a through glass via includes forming a plated through hole structure.”
Wang discloses, wherein forming a through glass via includes forming a plated through hole structure (“copper may be electroplated within the TGV 135 120 to form a copper pillar.”, ¶ 0044).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “wherein forming a through glass via includes forming a plated through hole structure”, as disclosed by Wang in the system of Shan, for the purpose of allowing for formation of high quality void free through electrical vias. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Shan et al. (US 2025/0210426) in view of Song (US 2024/0071943) in view of Shan et al. (US 2024/0213170, hereinafter referred to as “Shan ‘170”) in view of Soetan-Dodd et al. (US 2024/0332195, hereinafter referred to as ‘SD’).
Regarding claim 20, the prior art of Shan et al. disclose the method according to claim 16, however Shan does not disclose, “further comprising forming solder resist layers disposed on outermost surfaces of the first and second build up structures, and forming conductive terminals on the solder resist layers, wherein the conductive terminals on the first and the second build up structure are electrically connected with the first and second semiconductor dies and electrically connected with the electronic component.”
SD discloses in Fig. 1, further comprising forming solder resist layers (“Solder resist layers 103”, ¶ 0020) disposed on outermost surfaces of the first and second build up structures (The build up structures have already been shown in the rejections above in this chain of dependency, here the analogous placeholder of a substrate is element 101 with equivalent build up layers 102/117/115), and forming conductive terminals disposed on the solder resist layers (104/151, ¶ 0020), wherein the conductive terminals on the first and the second build up structure are electrically connected with the first and second semiconductor dies and electrically connected with the electronic component (151/104 are in an electrical pathway connecting to both of equivalent semiconductor dies 150, ¶ 0020).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “further comprising forming solder resist layers disposed on outermost surfaces of the first and second build up structures, and forming conductive terminals on the solder resist layers, wherein the conductive terminals on the first and the second build up structure are electrically connected with the first and second semiconductor dies and electrically connected with the electronic component”, as disclosed by SD in the system of Shan, for the purpose of providing insulation to the build up pads to prevent shorting while connection of the solder joints and insulate between the solder joints after formation. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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