DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species B, figures 8-9, claims 1, 3-4, 6-12, and 13 in the reply filed on August 7, 2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 5, 2025 was considered by the examiner.
Drawing Objections
The drawings are objected to because:
In figure 8, capacitor 130 needs to be labeled.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 8, 10, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jian et al. (CN 103915423 A) (“Jian”), in view of Mallik et al., “Chapter 22 Flip Chip Packaging for Nanoscale Silicon Logic Devices: Challenges and Opportunities”, Pgs. 491-516, Jan. 1, 2008, ISBN: 978-0-387-47325-3 (“Mallik”).
Regarding claim 1, Jian teaches at least in figures 2-8:
a substrate (1) having a first surface (side of 1 closes to 3/5; hereinafter A),
a second surface (side of 1 furthest from 3/5; hereinafter B) and an opening (2),
wherein the first surface (A) is opposite to the second surface (B);
a chip (3/5) located on the first surface (A) of the substrate (1) and in the opening (2) of the substrate (1);
a first molding compound (8 on top of 3; hereinafter C) covering the chip (3/5) and the first surface of the substrate (A); and
a second molding compound covering the second surface (8 on the bottom of 3/5 and contacting B; hereinafter D) of the substrate (1).
Jian does not teach:
a capacitor overlapping the chip in a vertical direction and electrically connected to the chip;
a second molding compound covering the capacitor and the second surface of the substrate.
Mallik teaches at least in figure 22.13:
a capacitor (decoupling capacitors; hereinafter E) overlapping the chip (Si Chip) in a vertical direction (E is below Si Chip) and electrically connected to the chip (pg. 502, where the decoupling capacitors are connected to the Si Chip’s power delivery).
It would have been obvious to one of ordinary skill in the art to add capacitors to the bottom of the substrate of Jian as this would allow one to decouple the chip closer to the chip. This would have the benefit of optimizing the power delivery path for minimal impedance. By adding the capacitor to the bottom of the substrate close to the chip one gets better power supply performance as compared to the a capacitor on the top side of the substrate. Pg. 502-503 at ¶ 1-3. Thus, it would have been obvious to one of ordinary skill in the art to combine Mallik with Jian to improve power delivery to the chip of Jian.
Regarding claim 3, the combination of prior art teaches:
wherein the capacitor (E) is surrounded by the substrate (1) (E would be surrounded by 1 in a plan view).
Regarding claim 4, the combination of prior art teaches:
wherein the second molding compound (D) has a portion between the capacitor (E) and the substrate (1).
Regarding claim 8, the combination of prior art teaches:
wherein the capacitor (E) is attached to the second surface of the substrate (B), and
the substrate (1) has a portion between the capacitor (E) and the chip (3/5) (E resides on B so a portion of 1 will be between E and 3/5).
Regarding claim 10, Jian teaches at least in figures 2-8:
a solder ball (9) located on the second surface (B) of the substrate (1).
Regarding claim 13, Jian teaches at least in figures 2-8:
Claim 13 contains the subject matter of claims 1 and 3, and is rejected for the same reasons as claims 1 and 3 above.
Claim(s) 9, and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jian, in view of Mallik, in view of official notice.
Regarding claim 9, the combination of prior art teaches:
wherein the chip (3/5) has a conductive pad (6),
the substrate (1) has a gold finger (detailed below),
the gold finger is located on the second surface and electrically connected to the capacitor (the gold finger is an electrical trace. It would be obvious that the substrate would have an electrical trace to the capacitor in order to make electrical contact to it), and
the semiconductor package further comprises (detailed below):
a conductive line (7) located in the second molding compound (D) and connecting the conductive pad (6) of the chip (3/5) and the gold finger (the electrical trace).
Examiner is taking official notice that this is how one of ordinary skill in the art would have connected the capacitor to the substrate by means of solder on gold finger pads, and then used Jian 7 to connect one side of the capacitor to the chip 3/5. The goal of the decoupling capacitor E is to be placed between power and ground as close to the chip as possible as taught by Millik. Therefore, as Jian teaches wire bonds it would have been obvious that the wire bonds would be used to make said connection. Further, it is standard practice in the industry to use metal such as gold or copper to act as bonding pads for components on a substrate. Thus, this limitation would have been obvious to one of ordinary skill in the art using routine skill in the art before the effective filing date of the current application.
Regarding claims 10-12,
The prior art does not teach the specific thickness/heights of the device of claim 1. However, the claimed ranges are well within the skill of one of ordinary skill in the art before the effective filing date of the current application. The thickness of the entire package structure is a result effective variable based upon the thicknesses of each of the elements which add to the total height. It would have been obvious to optimize the total height based upon industry standard expectations for said package structure. Therefore, the limitations of claims 11-12 would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claim 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the prior art does not teach:
wherein the second surface of the substrate has a step structure adjacent to the opening, and the capacitor is located on the step structure of the substrate.
This is because the prior art does not teach the claimed step structure.
Conclusion
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/VINCENT WALL/Primary Examiner, Art Unit 2898
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