DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to Arguments filed 7/6/2026.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1 and 3-5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (US 2019/0164966 A1).
Regarding claim 1, Wang discloses a semiconductor device (final device shown in Fig. 7), comprising:
a fin-shaped structure (112 in Fig. 7; fin structure more clearly seen in Fig. 1) extend along a first direction (direction of the length of the fin in Fig. 1) on a substrate (“substrate 110” in Figs. 1 and 7, ¶ 0012);
a gate electrode (“gate electrode 714” in Fig. 7, ¶ 0029) extend along in a second direction (direction of the length of the gate electrode in Fig. 7) on the fin-shaped structure (compare Figs. 1 and 7);
a spacer (712 in Fig. 7; compare to Applicant’s spacer 26 in Applicant’s Fig. 3) directly contacting sidewalls of the gate electrode (see Fig. 7); and
a gate dielectric layer (combination of 210 in Fig. 3 (which is a “dielectric layer” per ¶ 0019) and 310 in Fig. 3 (which is a “dielectric material” per ¶ 0019); although portion 210 is not shown in Fig. 7, Wang discloses layer 210 still remains in some embodiments (¶ 0027)) extending along the first direction (although the longest length of the gate dielectric is shown to be in the second direction in Fig. 3, the gate dielectric layer stretches in the first direction and is, therefore, considered to extend in the first direction) between the fin-shaped structure and the gate electrode (compare Figs. 1, 3, and 7), wherein the gate dielectric layer comprises a first portion (see rendering below) directly under the gate electrode and a second portion (see rendering below) adjacent to two sides of the gate electrode and directly under the spacer (see rendering below), the first portion directly under the gate electrode and the second portion directly under the spacer comprise different materials (first portion comprising silicon oxide per ¶ 0017 and the second portion comprising silicon oxynitride per ¶ 0019), and both the first portion and the second portion are adjacent to and directly contacting a sidewall of the fin-shaped structure (see Figs. 2 and 3) while the first portion, the second portion, and the fin-shaped structure are all extending along the first direction (although the longest length of the first and second portions are shown to be in the second direction in Fig. 7, the first and second portion stretch in the first direction and are, therefore, considered to extend in the first direction).
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Regarding claim 3, Wang discloses the semiconductor device of claim 2, as discussed above.
Wang further discloses wherein the first portion comprises silicon oxide (¶ 0017) and the second portion comprises silicon oxynitride (¶ 0019).
Regarding claim 4, Wang discloses the semiconductor device of claim 1, as discussed above.
Wang further discloses an epitaxial layer (420 in Fig. 7, ¶ 0021) adjacent to two sides of the gate electrode, wherein the second portion is between the first portion and the epitaxial layer (compare Fig. 7 of Wang and rendering, above)
Regarding claim 5, Wang discloses the semiconductor device of claim 1, as discussed above.
Wang further discloses wherein the first direction is orthogonal to the second direction (compare Figs. 1 and 7, above which show the second direction (direction of length of the gate electrode) orthogonal to the first direction (direction of length of the fin structure).
Response to Arguments
Applicant's arguments filed 7/6/2026 have been fully considered but they are not persuasive.
In Applicant’s previously submitted remarks (Remarks filed 12/3/2025) the Applicant identified the second portion of the gate dielectric layer as consisting only of a portion of 210. This is inconsistent with the mapping used in the Non-Final Rejection mailed 6/11/2025, the Final Rejection mailed 9/5/2025, the Non-Final Rejection mailed 4/8/2026, and the present Rejection, each of which included an annotated figure labeling the second portion as comprising part of 210 as well as 310.
The Examiner previously noted (see Response to Arguments mailed 4/8/2026) that Applicant’s mapping of what constitutes the two “portions” of the gate dielectric layer of Wang “is different from the mapping used” by the rejections.
In response, Applicant submits (Page 2, Line 28 of the newly submitted Remarks) that “Applicant’s position has remained consistent throughout prosecution”. Respectfully, the Examiner notes that the issue isn’t whether Applicant’s position is consistent with itself but, instead, that Applicant’s mapping is not consistent with the mapping of the Rejections. Specifically, Applicant’s Remarks state (Page 3 of the Remarks) that “the annotated figure shown below [which is the annotated figure used in the Rejections] identifies the ‘first portion’ as only the central portion of component 210 directly under gate electrode 714, while the ‘second portion’ is identified as the ‘remaining portion of the gate dielectric.’ Under such annotation, the ‘second portion’ necessarily includes not only layer 310 but also the remaining portions of component 210” (emphasis added).
As such, Applicant acknowledges that the annotation identifies that the second portion includes both 310 and parts of 210. However, Applicant follows this statement with “Accordingly, the annotated figure does not support an interpretation in which the second portion corresponds exclusively to layer 310.” This argument is not persuasive as Applicant has not given any indication as to where this “interpretation in which the second portion corresponds exclusively to layer 310” came from. It was not the position in either the present or any of the prior three Office actions which specifically point to the annotated rendering which, as acknowledged by Applicant, includes both 310 and part of 210. As such, Applicant’s argument uses a different mapping of the portions of Wang than used in the Rejections.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.C/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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