Prosecution Insights
Last updated: April 19, 2026
Application No. 18/653,933

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102
Filed
May 02, 2024
Examiner
CULBERT, CHRISTOPHER A
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
UNITED MICROELECTRONICS CORPORATION
OA Round
5 (Non-Final)
41%
Grant Probability
Moderate
5-6
OA Rounds
3y 8m
To Grant
46%
With Interview

Examiner Intelligence

Grants 41% of resolved cases
41%
Career Allow Rate
137 granted / 333 resolved
-26.9% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
81 currently pending
Career history
414
Total Applications
across all art units

Statute-Specific Performance

§103
55.8%
+15.8% vs TC avg
§102
20.9%
-19.1% vs TC avg
§112
22.1%
-17.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 333 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/3/2025 has been entered. Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1 and 3-5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang et al. (US 2019/0164966 A1). Regarding claim 1, Wang discloses a semiconductor device (final device shown in Fig. 7), comprising: a fin-shaped structure (112 in Fig. 7; fin structure more clearly seen in Fig. 1) extend along a first direction (direction of the length of the fin in Fig. 1) on a substrate (“substrate 110” in Figs. 1 and 7, ¶ 0012); a gate electrode (“gate electrode 714” in Fig. 7, ¶ 0029) extend along in a second direction (direction of the length of the gate electrode in Fig. 7) on the fin-shaped structure (compare Figs. 1 and 7); a spacer (712 in Fig. 7; compare to Applicant’s spacer 26 in Applicant’s Fig. 3) directly contacting sidewalls of the gate electrode (see Fig. 7); and a gate dielectric layer (combination of 210 in Fig. 3 (which is a “dielectric layer” per ¶ 0019) and 310 in Fig. 3 (which is a “dielectric material” per ¶ 0019); although portion 210 is not shown in Fig. 7, Wang discloses layer 210 still remains in some embodiments (¶ 0027)) extending along the first direction (although the longest length of the gate dielectric is shown to be in the second direction in Fig. 3, the gate dielectric layer stretches in the first direction and is, therefore, considered to extend in the first direction) between the fin-shaped structure and the gate electrode (compare Figs. 1, 3, and 7), wherein the gate dielectric layer comprises a first portion (see rendering below) directly under the gate electrode and a second portion (see rendering below) adjacent to two sides of the gate electrode and directly under the spacer (see rendering below), the first portion directly under the gate electrode and the second portion directly under the spacer comprise different materials (first portion comprising silicon oxide per ¶ 0017 and the second portion comprising silicon oxynitride per ¶ 0019), and both the first portion and the second portion are adjacent to and directly contacting a sidewall of the fin-shaped structure (see Figs. 2 and 3) while the first portion, the second portion, and the fin-shaped structure are all extending along the first direction (although the longest length of the first and second portions are shown to be in the second direction in Fig. 7, the first and second portion stretch in the first direction and are, therefore, considered to extend in the first direction). PNG media_image1.png 672 624 media_image1.png Greyscale Regarding claim 3, Wang discloses the semiconductor device of claim 2, as discussed above. Wang further discloses wherein the first portion comprises silicon oxide (¶ 0017) and the second portion comprises silicon oxynitride (¶ 0019). Regarding claim 4, Wang discloses the semiconductor device of claim 1, as discussed above. Wang further discloses an epitaxial layer (420 in Fig. 7, ¶ 0021) adjacent to two sides of the gate electrode, wherein the second portion is between the first portion and the epitaxial layer (compare Fig. 7 of Wang and rendering, above) Regarding claim 5, Wang discloses the semiconductor device of claim 1, as discussed above. Wang further discloses wherein the first direction is orthogonal to the second direction (compare Figs. 1 and 7, above which show the second direction (direction of length of the gate electrode) orthogonal to the first direction (direction of length of the fin structure). Response to Arguments Applicant's arguments filed 12/03/2025 have been fully considered but they are not persuasive. Applicant argues that the “first portion” and “second portion” of Wang fails to disclose the newly added limitations. Applicant’s mapping of what constitutes the “first portion” and what constitutes the “second portion” is different from the mapping used in both the present and prior Office actions. The mapping used in the Office actions is consistent with the newly added limitations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A CULBERT/Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

May 02, 2024
Application Filed
Nov 16, 2024
Non-Final Rejection — §102
Jan 07, 2025
Response Filed
Apr 13, 2025
Final Rejection — §102
Jun 05, 2025
Request for Continued Examination
Jun 09, 2025
Non-Final Rejection — §102
Jun 09, 2025
Response after Non-Final Action
Aug 27, 2025
Response Filed
Sep 02, 2025
Final Rejection — §102
Nov 04, 2025
Interview Requested
Dec 03, 2025
Request for Continued Examination
Dec 15, 2025
Response after Non-Final Action
Apr 04, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12557465
PHOTOELECTRIC DEVICE
2y 5m to grant Granted Feb 17, 2026
Patent 12532521
METHOD FOR MANUFACTURING SELF-ALIGNED EXCHANGE GATES AND ASSOCIATED SEMICONDUCTING DEVICE
2y 5m to grant Granted Jan 20, 2026
Patent 12520723
ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DEVICE INCLUDING THE SAME
2y 5m to grant Granted Jan 06, 2026
Patent 12512315
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 5m to grant Granted Dec 30, 2025
Patent 12501743
MICRO-LED STRUCTURE AND MICRO-LED CHIP INCLUDING SAME
2y 5m to grant Granted Dec 16, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
41%
Grant Probability
46%
With Interview (+4.4%)
3y 8m
Median Time to Grant
High
PTA Risk
Based on 333 resolved cases by this examiner. Grant probability derived from career allow rate.

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