DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the method group and claims 1-14 and 21-26 in the reply filed on 8/6/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hsin et al (U.S. Pub #2013/0026604), in view of Wakano et al (U.S. Pub #2020/0295218).
With respect to claim 1, Hsin teaches a method for forming a single-photon avalanche diode (SPAD) sensor, comprising:
doping a semiconductor substrate (Fig. 5, 202) to form a first well (Fig. 5, 210 and Paragraph 60);
patterning the semiconductor substrate to form a plurality of fin-like structures (Fig. 5, fin structures between isolation regions 203) and a mesa surrounding the plurality of fin-like structures (Fig. 5, area outside of region 200’);
forming a second well (Fig. 5, 204 and Paragraph 59) in the semiconductor substrate and in the fin-like structures; and
doping the second well to form a doped layer (Fig. 5, 206 and/or 208; Paragraph 57) in the fin-like structures and over the second well.
Hsin does not teach that the avalanche photodiode is a single photon avalanche photodiode.
Wakano teaches an avalanche photodiode comprising fin portions, wherein the device is configured as a single photon avalanche photodiode (Paragraph 2 and 69).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the avalanche photodiode of Hsin as a single photon avalanche photodiode as taught by Wakano in order to provide a high sensitivity device (Paragraph 2).
With respect to claim 2, Hsin teaches that the first well and the second well include a first conductivity type (Paragraph 59, n-type), and the doped layer includes a second conductivity type (Paragraph 59, p-type) complementary to the first conductivity type.
With respect to claim 6, Hsin teaches doping one of the plurality of fin-like structures to form a doped region (Fig. 5, 206), wherein the doped region and the doped layer comprise a same conductivity type (Fig. 5, i.e. multiple doped regions/layers 206).
With respect to claim 7, Hsin teaches doping the mesa to form a doped region (Fig. 7, 308 and Paragraph 64), wherein the doped region and the doped layer comprise a same conductivity type.
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8-14 and 21-26 are allowed.
The following is an examiner’s statement of reasons for allowance: the best prior art of record does not teach or fairly suggest
in claim 8:
doping a portion of the semiconductor substrate to form a first well in the second region;
patterning the semiconductor substrate to form a plurality of fin-like structures and a mesa surrounding the plurality of fin-like structures in the first region;
forming a second well in the fin-like structures and the semiconductor substrate in the first region;
doping the fin-like structures to form a doped layer over the second well in the first region;
…
doping one of the fin-like structures or a portion of the mesa to form a first doped region in the first region.
in claim 21:
forming a second well in the semiconductor substrate under the fin-like structures and coupled to the first well;
forming a third well in the fin-like structure and coupled to the second well; and
forming a doped layer in the fin-like structures and over the third well, wherein the first well, the second well and the third well comprise a first conductivity type, and the doped layer comprises a second conductivity type complementary to the first conductivity type.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN P SANDVIK/ Primary Examiner, Art Unit 2812
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