DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (6,214,653) in view of Rao (10,367,064).
Re claim 1, Chen et al. disclose a semiconductor substrate (101) (Fig. 1A); a plurality of buried spaced-apart insulator regions (102) in the semiconductor substrate (101); a monocrystalline semiconductor layer (103) on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the buried insulator regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions (Figs. 1B and 1C); and a plurality of semiconductor devices in the monocrystalline layer, with at least some of the semiconductor devices in the localized SOI regions, and at least some other semiconductor devices in the localized bulk semiconductor regions (Fig. 1D & Col. 3, lines 53-67).
Chen et al. does not disclose a superlattice in the monocrystalline semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Rao discloses a superlattice in the monocrystalline semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (Col. 5, lines 34-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Chen et al. and Rao to include the superlattice of Rao in the structure of Chen et al. because the superlattice reduce the effective mass of charge carrier and this thereby leads to higher charge carrier mobility (Col. 4, lines 32-34).
Re claim 2, Chen et al. disclose further comprising a plurality of spaced-apart isolated oxide regions (104) in the monocrystalline semiconductor layer (103).
Re claim 3, Chen et al. disclose wherein at least some of the isolated oxide regions extend downwardly to an adjacent buried insulator region (Fig. 1D).
Re claim 8, Chen et al. disclose further comprising at least one memory circuit die above the monocrystalline semiconductor layer and coupled with the plurality of semiconductor devices (Col. 2, lines 33-40).
Re claim 9, Rao discloses wherein the base semiconductor monolayers comprise silicon (Col. 3, lines 12-13).
Re claim 10, Rao discloses wherein the non-semiconductor monolayers comprise oxygen (Col. 3, lines 14-15).
Re claim 11, Chen et al. disclose wherein the buried insulator regions comprise an oxide (Col. 3, lines 39-41).
Re claim 12, Chen et al. disclose a semiconductor substrate (101); a plurality of buried spaced-apart oxide (BOX) regions (102) in the semiconductor substrate (Fig. 1A); a monocrystalline semiconductor layer (103) on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the BOX regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions (Figs. 1B & 1C); a superlattice in the monocrystalline semiconductor layer, the superlattice comprising; a plurality of semiconductor devices in the monocrystalline layer, with at least some of the semiconductor devices in the localized SOI regions, and at least some other semiconductor devices in the localized bulk semiconductor regions (Fig. 1D); and a plurality of spaced-apart isolated oxide regions (104) in the monocrystalline semiconductor layer (Fig. 1D).
Chen et al. does not disclose a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Rao discloses a superlattice in the monocrystalline semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (Col. 5, lines 34-45).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Chen et al. and Rao to include the superlattice of Rao in the structure of Chen et al. because the superlattice reduce the effective mass of charge carrier and this thereby leads to higher charge carrier mobility (Col. 4, lines 32-34).
Re claim 13, Chen et al. disclose wherein at least some of the isolated oxide regions extend downwardly to an adjacent buried insulator region (Fig. 1D).
Re claim 14, Chen et al. disclose further comprising at least one memory circuit die above the monocrystalline semiconductor layer and coupled with the plurality of semiconductor devices (Col. 2, lines 33-40).
Re claim 15, Rao discloses wherein the base semiconductor monolayers comprise silicon (Col. 3, lines 12-13), and wherein the non-semiconductor monolayers comprise oxygen (Col. 3, lines 14-15).
Claim(s) 4, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Rao as applied to claims 1-3 and 8-15 above, and further in view of Stephenson (2019/0319167).
Re claims 4 and 16, the combination does not disclose comprising a plurality of optical waveguides in the monocrystalline semiconductor layer.
Stephenson discloses a superlattice in a monocrystalline semiconductor layer (25); and a plurality of optical waveguides (67) in the monocrystalline semiconductor layer (25) (Fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Chen et al., Rao and Stephenson to include the optical waveguides of Stephenson in the combination to yield optoelectronic, structural and performance benefits for photonic integrated circuits.
Re claim 20, Rao discloses wherein the base semiconductor monolayers comprise silicon (Col. 3, lines 12-13), and wherein the non-semiconductor monolayers comprise oxygen (Col. 3, lines 14-15).
Allowable Subject Matter
Claims 5-7 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pending the correction of issues outlined in the rejection above, the following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest the following in combination the remaining limitations called for in each claim:
wherein the optical waveguides comprise an oxide, as recited in claim 5;
wherein the plurality of semiconductor devices comprises at least one of an optical detector and an optical source, as recited in claim 6;
wherein the plurality of waveguides comprises a plurality of levels of waveguides, as recited in claim 7;
wherein the plurality of semiconductor devices comprises at least one of an optical detector and an optical source, as recited in claim 17;
wherein the optical waveguides comprise an oxide, as recited in claim 18;
wherein the plurality of waveguides comprises a plurality of levels of waveguides, as recited in claim 19.
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2025/0089359 A1, US 2025/0126919 A1 and US 2024/0222514 A1 disclose a similar configuration for a semiconductor device with localized semiconductor on insulator regions.
Conclusion
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/MICHELLE MANDALA/ Primary Examiner, Art Unit 2893 September 15, 2026
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