DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-8 and 14-20 in the reply filed on 9/14/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Applicant has cancelled non-elected claims.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 and 14-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang et al. (US PGPub 2020/0194476, hereinafter referred to as “Chuang”).
Chuang discloses the semiconductor device as claimed. See figures 1-5 and corresponding text, where Chuang teaches, in claim 1, a semiconductor device, comprising: (figures 1 and 2; [0027-0044])
a poly layer (103-21, 103-22);
a substrate (101) over the poly layer (103-21, 103-22);
a first epitaxial layer (102) over the substrate (101);
a second epitaxial layer (105) over the first epitaxial layer (102); and
a photodiode (103) in at least one of the first epitaxial layer (102) or the second epitaxial layer (105).
Chuang teaches, in claim 2, wherein: the poly layer comprises polysilicon ([0029]).
Chuang teaches, in claim 3, comprising:
an oxide layer under the poly layer ([0029]).
Chuang teaches, in claim 4, wherein:
a first thickness of the first epitaxial layer is less than a second thickness of the second epitaxial layer ([0028]).
Chuang teaches, in claim 5, wherein: (figures 1 and 2; [0027-0044])
the substrate comprises first dopants having a first conductivity type;
the first epitaxial layer comprises second dopants having the first conductivity type;
the second epitaxial layer comprises third dopants having the first conductivity type; and the photodiode comprises:
a first doped region comprising fourth dopants having a second conductivity type different than the first conductivity type; and
a second doped region, over the first doped region, comprising fifth dopants having the first conductivity type.
Chuang teaches, in claim 6, wherein the photodiode comprises:
a p-n junction between the first doped region and the second doped region (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 7, wherein the photodiode comprises:
an intrinsic region between the first doped region and the second doped region (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 8, wherein: (figures 1 and 2; [0027-0044])
a first concentration of the second dopants in the first epitaxial layer is greater than a second concentration of the third dopants in the second epitaxial layer.
Chuang teaches, in claim 14, a semiconductor device, comprising:
a poly layer (103-21, 103-22);
a substrate (101) over the poly layer;
an epitaxial layer (102, 105) over the substrate, wherein a thickness of the poly layer is less than a thickness of the epitaxial layer; and
a photodiode in the epitaxial layer (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 15, wherein:
the poly layer comprises polysilicon ([0029]).
Chuang teaches, in claim 16, comprising:
an oxide layer under the poly layer ([0029]).
Chuang teaches, in claim 17, wherein:
the substrate comprises first dopants having a first conductivity type;
the epitaxial layer comprises second dopants having the first conductivity type; and the photodiode comprises:
a first doped region comprising third dopants having a second conductivity type different than the first conductivity type; and
a second doped region, over the first doped region, comprising fourth dopants having the first conductivity type (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 18, wherein the photodiode comprises: a p-n junction between the first doped region and the second doped region (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 19, wherein the photodiode comprises:
an intrinsic region between the first doped region and the second doped region (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 20, wherein:
the first conductivity type is p-type; and the second conductivity type is n-type (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 21, a semiconductor device, comprising:
a poly layer (103-21, 103-22) disposed at a first side of a substrate (101);
a first epitaxial layer (102) over the substrate, wherein the substrate is between the first epitaxial layer (102) and the poly layer;
a second epitaxial layer (105) over the first epitaxial layer (102); and
a photodiode (103) in at least one of the first epitaxial layer or the second epitaxial layer (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 22, wherein: the substrate comprises first dopants having a first conductivity type;
the first epitaxial layer comprises second dopants having the first conductivity type; the second epitaxial layer comprises third dopants having the first conductivity type; and the photodiode comprises:
a first doped region comprising fourth dopants having a second conductivity type in at least one of the first epitaxial layer or the second epitaxial layer, wherein the second conductivity type is different than the first conductivity type; and
a second doped region comprising fifth dopants having the first conductivity type in at least one of the first epitaxial layer or the second epitaxial layer, wherein the second doped region is over the first doped region (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 23, wherein:
the substrate comprises a first concentration of first dopants having a first conductivity type;
the first epitaxial layer comprises a second concentration of second dopants having the first conductivity type; and
the second epitaxial layer comprises a third concentration of third dopants having the first conductivity type, wherein the second concentration is greater than the third concentration (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 24, wherein the first epitaxial layer has a first thickness that is less than a second thickness of the second epitaxial layer (figures 1 and 2; [0027-0044]).
Chuang teaches, in claim 25, wherein the poly layer comprises polysilicon ([0029]).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 September 30, 2026
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