DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 16 is objected to because of the following informalities: in line 7, replace the word “box” with --BOX-- for conformity with its previously established status as an acronym. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 8-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (USPN 6,214,653) in view of Rao (USPN 10,367,064).
Regarding claim 1, Chen et al disclose a method for making a semiconductor device comprising:
forming a plurality of buried spaced-apart insulator regions 102 in a semiconductor substrate 101 [see Fig. 1A; see also col. 3, lines 39-41];
forming a monocrystalline semiconductor layer 103 on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the buried insulator regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions [see Figs. 1B and 1C; see also col. 3, lines 46-52]; and
forming a plurality of semiconductor devices in the monocrystalline layer, with at least some of the semiconductor devices in the localized SOI regions, and at least some other semiconductor devices in the localized bulk semiconductor regions [see Fig. 1D; see also col. 3, lines 53-67].
Chen et al do not disclose forming a superlattice in the monocrystalline semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. One such as Rao discloses the use of a superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions [see col. 5, lines 34-43]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the superlattice of Rao in the method of Chen et al because Rao teaches that the superlattice described thereby reduce the effective mass of charge carrier and thereby provide higher charge carrier mobility [see col. 4, lines 32-34].
Regarding claim 2, the prior art of Chen et al and Rao disclose the method of claim 1. Furthermore, Chen et al disclose comprising forming a plurality of spaced-apart isolated oxide regions 104 in the monocrystalline semiconductor layer [see Fig. 1D; see also col. 3, lines 53-56].
Regarding claim 3, the prior art of Chen et al and Rao disclose the method of claim 2. Furthermore, Chen et al disclose wherein at least some of the isolated oxide regions extend downwardly to an adjacent buried insulator region [see Fig. 1D].
Regarding claim 8, the prior art of Chen et al and Rao disclose the method of claim 1. Furthermore, Chen et al disclose comprising positioning at least one memory circuit die above the monocrystalline semiconductor layer and coupled with the plurality of semiconductor devices [see col. 2, lines 34-40].
Regarding claims 9 and 10, the prior art of Chen et al and Rao disclose the method of claim 1. Furthermore to the superlattice, Rao discloses wherein the base semiconductor monolayers comprise silicon, and wherein the non-semiconductor monolayers comprise oxygen [see col. 3, lines 12-15].
Regarding claim 11, the prior art of Chen et al and Rao disclose the method of claim 1. Furthermore, Chen et al disclose wherein the buried insulator regions comprise an oxide [see col. 3, lines 39-41].
Regarding claim 12, Chen et al disclose a method for making a semiconductor device comprising:
forming a plurality of buried spaced-apart oxide (BOX) regions 102 in a semiconductor substrate 101 [see Fig. 1A; see also col. 3, lines 39-41];
forming a monocrystalline semiconductor layer 103 on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the BOX regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions [see Figs. 1B and 1C; see also col. 3, lines 46-52];
forming a plurality of semiconductor devices in the monocrystalline layer, with at least some of the semiconductor devices in the localized SOI regions, and at least some other semiconductor devices in the localized bulk semiconductor regions [see Fig. 1D; see also col. 3, lines 53-67]; and
forming a plurality of spaced-apart isolated oxide regions 104 in the monocrystalline semiconductor layer [see Fig. 1D; see also col. 3, lines 53-56].
Chen et al do not disclose forming a superlattice in the monocrystalline semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. One such as Rao discloses the use of a superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions [see col. 5, lines 34-43]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the superlattice of Rao in the method of Chen et al because Rao teaches that the superlattice described thereby reduce the effective mass of charge carrier and thereby provide higher charge carrier mobility [see col. 4, lines 32-34].
Regarding claim 13, the prior art of Chen et al and Rao disclose the method of claim 12. Furthermore, Chen et al disclose wherein at least some of the isolated oxide regions extend downwardly to an adjacent buried insulator region [see Fig. 1D].
Regarding claim 14, the prior art of Chen et al and Rao disclose the method of claim 12. Furthermore, Chen et al disclose comprising positioning at least one memory circuit die above the monocrystalline semiconductor layer and coupled with the plurality of semiconductor devices [see col. 2, lines 34-40].
Regarding claim 15, the prior art of Chen et al and Rao disclose the method of claim 12. Furthermore to the superlattice, Rao discloses wherein the base semiconductor monolayers comprise silicon, and wherein the non-semiconductor monolayers comprise oxygen [see col. 3, lines 12-15].
Claims 4, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (USPN 6,214,653) in view of Rao (USPN 10,367,064) as applied to claim 1 above, and further in view of Stephenson (US Patent Application Publication 2019/0319167).
Regarding claim 4, the prior art of Chen et al and Rao disclose the method of claim 1. Neither Chen et al nor Rao disclose comprising forming a plurality of optical waveguides in the monocrystalline semiconductor layer. One such as Stephenson discloses forming a superlattice in a monocrystalline semiconductor layer 25, as disclosed by Chen et al as modified by Rao, furthermore comprising forming a plurality of optical waveguides 67 in the monocrystalline semiconductor layer [see Fig. 5; see also paragraphs 0056 and 0057]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the optical waveguides of Stephenson in the method of Chen et al, as modified by Rao, in order to confine and guide light emitted by the structure formed by the method.
Regarding claim 16, Chen et al disclose a method for making a semiconductor device comprising:
forming a plurality of buried spaced-apart oxide (BOX) regions 102 in a semiconductor substrate 101 [see Fig. 1A; see also col. 3, lines 39-41];
forming a monocrystalline semiconductor layer 103 on the semiconductor substrate defining respective localized semiconductor on insulator (SOI) regions above the BOX regions, and respective localized bulk semiconductor regions laterally between adjacent SOI regions [see Figs. 1B and 1C; see also col. 3, lines 46-52]; and
forming a plurality of semiconductor devices in the monocrystalline layer, with at least some of the semiconductor devices in the localized SOI regions, and at least some other semiconductor devices in the localized bulk semiconductor regions [see Fig. 1D; see also col. 3, lines 53-67].
Chen et al do not disclose forming a superlattice in the monocrystalline semiconductor layer, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, nor forming a plurality of optical waveguides in the monocrystalline semiconductor layer.
One such as Rao discloses the use of a superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions [see col. 5, lines 34-43]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the superlattice of Rao in the method of Chen et al because Rao teaches that the superlattice described thereby reduce the effective mass of charge carrier and thereby provide higher charge carrier mobility [see col. 4, lines 32-34].
Neither Chen et al nor Rao disclose comprising forming a plurality of optical waveguides in the monocrystalline semiconductor layer. One such as Stephenson discloses forming a superlattice in a monocrystalline semiconductor layer 25, as disclosed by Chen et al as modified by Rao, furthermore comprising forming a plurality of optical waveguides 67 in the monocrystalline semiconductor layer [see Fig. 5; see also paragraphs 0056 and 0057]. It would have been obvious to one of ordinary skill in the art at the time of invention to include the optical waveguides of Stephenson in the method of Chen et al, as modified by Rao, in order to confine and guide light emitted by the structure formed by the method.
Regarding claim 20, the prior art of Chen et al, Rao and Stephenson disclose the method of claim 16. Furthermore to the superlattice, Rao discloses wherein the base semiconductor monolayers comprise silicon, and wherein the non-semiconductor monolayers comprise oxygen [see col. 3, lines 12-15].
Allowable Subject Matter
Claims 5-7 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding dependent claims 5 and 18, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein the optical waveguides comprise an oxide; regarding dependent claims 6 and 17, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein the plurality of semiconductor devices comprises forming at least one of an optical detector and an optical source; regarding dependent claims 7 and 19, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein forming the plurality of waveguides comprises forming a plurality of levels of waveguides.
Conclusion
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/C.E.S./Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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