DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 05/03/2024.
Claims 1-10 are pending in this application.
Foreign Priority
2. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Waite et al. (US 6,972,478)
Regarding claim 1, Waite discloses a method for improving Fully Depleted Silicon-on-Insulator (FDSOI) device leakage, at least comprising:
step 1, providing a semiconductor structure (shown in fig. 4), wherein the semiconductor structure comprises:
a silicon substrate 24 or 22&24, a buried oxide layer 30, a silicon-on-insulator (SOI) layer 26, a first oxide layer36, and a silicon nitride layer 38, formed sequentially from bottom to top on the silicon substrate 22/24;
step 2, defining a bulk silicon region (where trench 42, or trench 46 being formed, fig. 5, fig. 7) on the semiconductor structure, and forming a recess area 42, 46 in the bulk silicon region by removing the silicon nitride layer 38, the first oxide layer 36, the SOI layer 26, and the buried oxide layer 30 in the bulk silicon region by etch, wherein the etch is stopped at the silicon substrate 22/24;
step 3, refilling the recess area 42, 46 in the bulk silicon region with monocrystalline silicon 49, 50 (see col. 4, lines 40-59: selective epitaxial grow of silicon layer 49 in the recess area 42 with the <110> crystalline orientation, or silicon layer 50 in the recess area 46 with the <100> crystalline orientation), until the monocrystalline silicon 49, 50 reaches a same height as a height of the SOI layer 26 outside of the bulk silicon region (fig. 9, fig. 13), wherein after the refilling the recess area 42, 46 with the monocrystalline silicon 49, 50, the silicon nitride layer 38 and the first oxide layer 36 outside the bulk silicon region are removed (fig. 13; col. 6, lines 1-10);
step 4, forming shallow trench isolation (STI) regions 85/60 (fig. 11/fig. 12) inside a non-bulk silicon region and at a border between the non-bulk silicon region and the bulk silicon region; and
performing ion implantation on the bulk silicon region (col. 5, lines 23-67); and
step 5, forming a device structure 64, 66 (fig. 13) in the bulk silicon region.
Regarding claim 2, Waite discloses the method for improving the FDSOI device leakage according to claim 1, wherein the bulk silicon region is defined on the semiconductor structure in step 2 by means of photolithography. See col. 3, line 62 – col. 4, line 33; col. 7, lines 10-29.
Regarding claim 3, Waite discloses the method for improving the FDSOI device leakage according to claim 2, wherein defining the bulk silicon region by means of photolithography in step 2 further comprises:
applying a layer of photoresist 40 on the semiconductor structure by spin-coating, followed by exposure and development, wherein photoresist on an upper surface of the semiconductor structure defining the bulk silicon region is removed, and photoresist on the upper surface of the semiconductor structure outside the bulk silicon region is retained. See col. 3, line 62 – col. 4, line 33; col. 7, lines 10-29.
Regarding claim 4, Waite discloses the method for improving the FDSOI device leakage according to claim 3, wherein in step 2, the removing the silicon nitride layer 38, the first oxide layer 36, the SOI layer 36, and the buried oxide layer 30 in the bulk silicon region by etch further comprises:
etching the silicon nitride layer, the first oxide layer, the SOI layer, and the buried oxide layer sequentially downward from the upper surface of the semiconductor structure that is not covered by the photoresist 40. See fig. 6, fig. 7.
Regarding claim 5, Waite discloses the method for improving the FDSOI device leakage according to claim 3, wherein in step 3, the refilling the recess area 42, 46 with the monocrystalline silicon 49, 50 further comprises performing backfilling with selective non-doped intrinsic silicon. See col. 5, lines 23-67.
Regarding claim 6, Waite discloses the method for improving the FDSOI device leakage according to claim 1, wherein in step 4, the forming the STI regions further comprises:
forming a first trench 58 in the non-bulk silicon region and a second trench 58 at the border between the non-bulk silicon region and the bulk silicon region;
forming a second oxide layer 59 on a surface of the SOI layer in the non-bulk silicon region, and on the surface of the monocrystalline silicon in the bulk silicon region; and
filling the first and the second trenches with a silicon oxide material 59 to form the STI regions 60. See figs. 11, 12.
Regarding claim 7, Waite discloses the method for improving the FDSOI device leakage according to claim 1, wherein a dose of the ion implantation on the bulk silicon region in step 4 is in a range of 5E11-5E13, and an implantation energy is in a range of 5 KEV-30 KEV. See col. 5, lines 40-67.
Regarding claim 8, Waite discloses the method for improving the FDSOI device leakage according to claim 1, wherein in step 4, the STI regions 60 are formed first, followed by performing the ion implantation on the bulk silicon region. See figs. 12, 13, and col. 5, lines 40-67.
Regarding claim 10, Waite discloses the method for improving the FDSOI device leakage according to claim 1, wherein devices formed in the bulk silicon region in step 5 comprise one or more of a Lateral Diffusion MOS (LDMOS), a diode, a resistor, a capacitor, and a substrate pick-up structure. See col. 5, lines 40-67.
Claim Rejections - 35 U.S.C. § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Waite et al. (US 6,972,478)
Regarding claim 9, Waite discloses the method for improving the FDSOI device leakage according to claim 1, comprising all claimed limitations, as discussed above.
Waite does not particularly teach that wherein in step 4, the ion implantation is
performed in the bulk silicon region first, followed by forming the STI region.
However, it would have been obvious to one of ordinary skills in the art at the time the invention was made that the claimed feature in this claim is just an obvious variance from the claimed feature of claim 8, that selecting which one between the STI regions and the ion implantation being performed first would involve only routine skills in the art. Should Applicant believe that these claimed features are patentably distinct from one and another, Applicant is required to select a single feature for further prosecution.
Conclusion
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 June 24, 2026
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