DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of invention I, claims 1-12 in the reply filed on August 19th 2026, with traverse, is acknowledged. However, since no argument was made for why the USPTO has not met its burden in supporting the restriction, the application is considered to be elected without traverse. Therefore claims 13-16 are hereby withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 is unclear because it is claiming an electronic package formed using the packaging method according to any one of claims 1 to 11, but it is unclear what exact structure is being claimed here. As an example, in claim 1, a second photoresist pattern is applied and then removed, so what actual device and associated structure is being referenced in claim 12 (the one before or after the photoresist pattern is removed). See also MPEP 2113 as to how product by process claims are examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sang-wook et al. (KR 100325459 B1) in view of Yoo et al. (US 2015/0228507 A1).
Regarding claim 1, Sang-wook et al. teaches a packaging method, comprising
forming on a carrier film a first photoresist pattern having multiple sets of first openings (Fig 7A shows a photoresist, 90, with a plurality of openings, 81);
filling in the multiple sets of first openings of the first photoresist pattern with a solder material to form multiple sets of solder bumps (Fig 7d shows the openings, 81, being filled with the bumps, 50);
filling in second openings with an encapsulant material to form an encapsulant layer that at least partially encapsulates the one or more electronic components in each of the second openings (the change from Fig 8b to Fig 9A shows the space around each of the electronic components relating to the openings, 20, being filled by the encapsulant, 120); and
form multiple electronic packages (Fig 9a shows multiple electronic packages formed from the process).
Sang-wook et al. does not teach forming on the first photoresist pattern a second photoresist pattern having multiple second openings each exposing a set of the sets of solder bumps;
attaching one or more electronic components to the set of solder bumps in each of the second openings;
filling in the second openings of the second photoresist patterns with an encapsulant material; and
removing the second photoresist pattern from the carrier film.
Yoo et al. teaches forming on the first photoresist pattern a second photoresist pattern having multiple second openings each exposing a set of the sets of solder bumps (Yoo et al. shows in Fig 3d a photoresist layer, 230’, in which there is an opening between the films, and additional openings on the other side of the film - to the right of the right most film and left of the left most film.);
attaching one or more electronic components to the set of solder bumps in each of the second openings (Fig 3e shows a semiconductor chip, 110, placed in the second opening between the photoresist pattern, 230’, the die attached to solder bumps, 212);
filling in second openings of a second photoresist pattern with an encapsulant material to form an encapsulant layer that at least partially encapsulates the one or more electronic components in each of the second openings (Fig 3f has molding portion/encapsulant placed inside the hole, 250 [though it is only labeled in Fig 3g], paragraph 52);
removing the second photoresist pattern from the carrier film (Fig 3g shows the photoresist pattern, 230’, being removed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sang-wook et al. to add a second photoresist pattern on top of the first photoresist layer to expose the solder bumps, then placing an electronic component in each of the openings, as taught in Yoo et al., because forming a photoresist pattern then placing the electronic components into the openings serves as protection for the electronic component, minimizing the damage to the electronic component during the assembly of the package.
It would further have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sang-wook et al. to then remove the photoresist pattern from the carrier film, as taught in Yoo et al., because removing the photoresist helps maintain surface quality of subsequent layers, allowing subsequent added layers to be formed more uniformly, increasing overall functionality of the semiconductor device.
The idea for the combination of Sang-wook with Yoo et al. is that Sang-wook teaches multiple electric components and Yoo et al. only shows one electric component with an upper layer (equivalent to second layer of photoresist as claimed) of photoresist formed on each side of the one component before the electric component is placed, so in the combination Yoo et al. would teach Sang-wook to put this upper photoresist on each side of the multiple electric components. The teaching of Yoo et al., placing the upper layer of photoresist, would be above the first photoresist of Sang-wook et al. and would expose the solder bumps, 50, within Sang-wook et al. (similar to how 201 and 212 are exposed in Yoo et al. in figures 3d and 3e) as the openings in the upper layer of photoresist would correspond to the location of each of the semiconductor chips, 20, in Sang-wook et al. The last step of Yoo et al. of removing the upper photoresist layer, once taught into the teaching of Sang-wook et al. would form multiple electric packages.
Regarding claim 2, Sang-wook et al., as modified, teaches before removing the second photoresist pattern from the carrier film, forming a shielding layer on each of the encapsulant layers (Fig 9A shows a mold, 110, formed over the encapsulant, 120, which serves to shield the encapsulant and the electronic components. The shielding layer would be formed before the modification of removing the photoresist of Yoo et al. done in claim 1).
Regarding claim 3, Sang-wook et al., as modified, teaches after removing the second photoresist pattern from the carrier film, detaching the electronic packages from the carrier film (Paragraph 61 describes the carrier film, 80, being detached from the rest of the electronic package. The removal of the carrier film would be after the modification of removing the photoresist of Yoo et al. done in claim 1).
Regarding claim 4, Sang wook et al., as modified, does not explicitly teach at least two of the second openings having different sizes or shapes as the combination described above in claim 1 and below in claim 5 would result in the openings being the same size.
MPEP 2144.04 IV A and B describe: (A) Changes in size/proportion, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (B) Changes in Shape - In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sang-wook et al. to have the second openings be different sizes or shapes, as taught in Yoo et al., because different sized openings enable multi-pattern strategies which allow for better flexibility which better allows for the manufacturing of smaller, denser packages.
Regarding claim 5, Sang-wook et al., as modified, teaches at least two of the second openings have the same size and shape (As the modifications made in claim 1 with Yoo et al. would have the openings fit the semiconductor chips, 20, of Sang-wook et al. the openings of the second photoresist taught in by Yoo et al. would be the same shape and size, as shown by the semiconductor package in Fig 9A of Sang-wook et al.).
Regarding claim 7, Sang-wook et al., as modified, teaches the encapsulant being formed over and besides the one or more electronic components in each of the second openings (Fig 9A shows the encapsulant, 120, surrounding the edges and the top surface of the semiconductor die).
Regarding claim 12, Sang-wook et al., as modified, teaches an electronic package formed using the packaging method according to claims 1-5 and 7 rejected above (Each of the claims above contain an electronic package which would have been formed with the method described in the rejected claims above).
Claims 6 & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sang-wook et al. (KR 100325459 B1) in view of Yoo et al. (US 2015/0228507 A1) as applied to claim 1 above, and further in view of Luan (US 20220165699 A1)
Regarding claim 6, Sang-wook et al., as modified, does not teach the carrier film is an adhesive film attached onto a carrier.
Luan teaches the carrier film is an adhesive film attached onto a carrier (Paragraph 0108 describes an adhesive, 522, that is attached to a carrier, 524. Fig 13 shows that the solder bumps are attached to the adhesive film, 522, on the temporary carrier, 524).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sang-wook et al. to make the carrier film an adhesive film attached to the carrier, as taught in Luan, because it would ensure that the package sticks together and that the carrier film does not peel off.
Regarding claim 12, Sang-wook et al., as modified, teaches an electronic package formed using the packaging method according to claim 6 rejected above (Claim 6 above contains an electronic package which would have been formed with the method described in the rejected claims above).
Claims 8 & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sang-wook et al. (KR 100325459 B1) in view of Yoo et al. (US 2015/0228507 A1) as applied to claim 1 above, and further in view of Chen et al. (US 20200006181 A1).
Regarding Claim 8 Sang-wook et al teaches the encapsulant layer being formed besides the one or more electronic components in each of the second openings (Fig 9A shows the encapsulant, 120, surrounding the edges of the semiconductor die).
Sang-wook et al., as modifed, does not teach exposing a top surface of at least one of the one or more electronic components.
Chen et al. teaches exposing a top surface of at least one of the one or more electronic components (Fig 5 shows an encapsulant, 302, surrounding the sides of the die stacks, 106A and 106B, and shows that the top surfaces of these dies are exposed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Sang-wook et al. to remove a portion of the encapsulant to expose one or more of the electrical components, as taught in Chen et al., because exposing the top surface of an electrical component in allows for the design of thinner packages without sacrificing electrical connectivity.
Regarding claim 12, Sang-wook et al., as modified, teaches an electronic package formed using the packaging method according to claim 8 rejected above (Claim 8 above contains an electronic package which would have been formed with the method described in the rejected claims above).
Allowable Subject Matter
Claims 9-11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
While the Sang-wook et al. modified by Yoo et al. does teach that the electrical components are dies as they use semiconductor chips which would contain semiconductor dies. However, they do not teach forming on the second photoresist pattern a third photoresist pattern having a third opening, wherein the third opening exposes a top surface of the semiconductor die; and forming in the third opening a dielectric material to cover the exposed top surface of the semiconductor die. Instead, it has an encapsulant covering the topside surface of the electrical components.
With the current rejection for claim 1 it would not be obvious to modify Sang-wook et al. because it would require not only removing the encapsulant on the top surface but also adding the further steps of forming a photoresist where the encapsulant was before, creating openings, before finally forming a dielectric material within the openings. This would require too many modifications for it to be considered obvious to one with ordinary skill in the art.
Claims 10-11 are also objected to using the reasoning above due to their dependence on claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Oh et al. (US 20050208751 A1) has a photoresist layer on top of an adhesion subsequently has a plurality of openings in which the solder bumps are used to fill the holes.
Cai et al. (US 9,875,977 B2) has a photoresist layer formed above electronic component with the dielectric layer with openings formed. This is then removed before an insulating layer is placed above the semiconductor component, including the area where the openings were
Olson et al. (US 20200402941 A1) Has a second photoresist layer formed over the first photoresist region. It shows the holes of the second photoresist region being formed over the openings of the first photoresist pattern which is above a carrier which is later removed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLOTTE ELIZABETH HARBOTTLE whose telephone number is (571)270-0644. The examiner can normally be reached Monday-Friday 7:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.E.H./Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights