DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7 and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al [US 2014/0103403].
With respect to claim 1, KIM et al (fig. 17) discloses an integrated chip, comprising:
a gate dielectric structure (21, 60a, pp [0021]; [0027]-[0028]) on a semiconductor substrate (10, pp [0019]); and
a gate electrode structure on the gate dielectric structure, wherein the gate electrode structure comprises a lower conductive structure (70a, pp [0027]-[0029]; [0037]) and a gate body structure (100, pp [0050]-[0055]), wherein the gate body structure comprises an upper segment (110, pp [0057]) over a top surface of the lower conductive structure (70a, pp [0027]-[0029]) and a lower segment (100, pp [0050]-[0055]) disposed between opposing inner sidewalls of the lower conductive structure (70a, pp [0027]-[0029]).
With respect to claim 2, KIM et al (fig. 17) discloses wherein the upper segment (100, pp [0050]-[0055]) comprises a first conductive material (100, pp [0050]-[0055]) and the lower segment (100, pp [0050]-[0055]) comprises a second conductive material (100, pp [0050]-[0055]) different from the first conductive material.
With respect to claim 7, KIM et al (fig. 17) discloses wherein top surfaces of the first and second conductive layers (70a, pp [0027]-[0029]; [0037]) are aligned and define the top surface of the lower conductive structure.
With respect to claim 26, KIM et al (fig. 17) discloses wherein a bottommost surface of the upper segment (100, pp [0050]-[0055]) is vertically spaced above the top surface of the lower conductive structure (70a, pp [0027]-[0029]; [0037]) by a first distance greater than a thickness of the second conductive layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al [US 2014/0103403] in view of Yang et al [US 2013/0049924].
With respect to claim 21, KIM et al (fig. 17) discloses an integrated chip, comprising:
a gate dielectric structure (21, 60a, pp [0021]; [0027]-[0028]) over a semiconductor substrate (10, pp [0019]);
a gate electrode over the gate dielectric structure, wherein the gate electrode comprises a conductive structure (70a, pp [0027]-[0029]; [0037]), a first gate layer (100, pp [0050]-[0055]), and a second gate layer (110, pp [0054]-[0057]), wherein the conductive structure (70a, pp [0027]-[0029]; [0037]) comprises a first conductive layer and a second conductive layer, wherein top surfaces of the first and second conductive layers define a top surface of the conductive structure, wherein the first conductive layer comprises a first material and the second conductive layer comprises a second material different from the first material,
wherein the first gate layer (100, pp [0050]-[0055]) extends along the top surface of the conductive structure and contacts inner sidewalls of the conductive structure, wherein the second gate layer overlies the first gate layer.
KIM et al do not mention a pair of source/drain regions on opposing sides of the gate dielectric structure. However, a pair of source/drain regions on opposing sides of the gate dielectric structure is well known in the art. Yang et al (fig. 8) disclose a pair of source/drain regions (126, pp [0020]) on opposing sides of the gate dielectric structure (107, pp [0020]; 150, pp [0022]). Therefore, it would have been obvious to one skill in the art to have the pair of source/drain regions as taught by Yang et al into the device of KIM et al in order for the gate to operate.
With respect to claim 22, KIM et al (fig. 17) discloses wherein a width of the first gate layer (100, pp [0050]-[0055]) between the inner sidewalls of the conductive structure (70a, pp [0027]-[0029]; [0037]) is greater than a lateral thickness of the conductive structure along a sidewall of the first gate layer.
With respect to claim 23, KIM et al (fig. 17) discloses wherein the first gate layer (100, pp [0050]-[0055]) comprises a first conductive material and the second gate layer (110, pp [0054]-[0057]) comprises a second conductive material different from the first conductive material, wherein the first and second conductive materials are different from materials of the first and second conductive layers.
With respect to claim 25, KIM et al (fig. 17) discloses wherein a first vertical distance between the top surface of the conductive structure (70b, pp [0027]-[0029]; [0037]) and a bottom surface of the second gate layer (110b) is less than a second vertical distance between a bottom surface of the first gate layer (100b) and a top surface of the gate dielectric structure (31).
Claims 3-5, 8 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al [US 2014/0103403] in view of Thirupapuliyur et al [US 2006/0289900].
With respect to claim 3, KIM et al fail to disclose wherein the first conductive material is a silicide of the second conductive material. However, Thirupapuliyur et al disclose (fig. 2) disclose wherein the first conductive material (122, pp [0023]) is a silicide of the second conductive material. Therefore, it would have been obvious to one skill in the art to have silicide as taught by Thirupapuliyur et al into the device of KIM et al in order to decrease the resistance of the gate.
With respect to claim 4, KIM et al (fig. 17) discloses wherein the lower segment (100, pp [0050]-[0055]) is T- shaped and has a lower surface in physical contact with the top surface of the lower conductive structure.
With respect to claim 5, KIM et al (fig. 17) discloses wherein a height of the upper segment (110, pp [0054]-[0057]) is less than a height of the lower segment (100, pp [0050]-[0055]).
With respect to claim 8, KIM et al (fig. 17) discloses further comprising: a sidewall spacer (117, pp [0030]) abutting a sidewall of the gate electrode structure, wherein the sidewall spacer comprises a first dielectric layer and a second dielectric layer, wherein the second dielectric layer comprises an L-shaped segment laterally spaced from the gate body structure by a thickness of the first dielectric layer. **Notice: as interpreting the claim in a broad scope, the first dielectric layer can also be the same as the second dielectric layer because the claim does not recite the different material between the first and second dielectric layers.
Claims 9-10 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al [US 2013/0049924] in view of Thirupapuliyur et al [US 2006/0289900].
With respect to claim 9, Yang et al (fig. 8) discloses an integrated chip, comprising:
a gate dielectric structure (107, 150, pp [0019]; [0022]) on a semiconductor substrate (100, pp [0019]);
a pair of source/drain regions (126, pp [0020]) in the semiconductor substrate and on opposing sides of the gate dielectric structure; and
a conductive gate layer (156, pp [0026]) on the lower conductive structure (152, pp [0023]), and wherein inner sidewalls of the lower conductive structure contact first opposing sidewalls of the conductive gate layer.
Yang et al fail to disclose a silicide layer on the conductive gate layer, wherein opposing sidewalls of the silicide layer are aligned with opposing sidewalls of the lower conductive structure. However, Thirupapuliyur et al disclose (fig. 2) a silicide layer on the conductive gate layer (122, pp [0023]), wherein opposing sidewalls of the silicide layer are aligned with opposing sidewalls of the lower conductive structure. Therefore, it would have been obvious to one skill in the art to have silicide as taught by Thirupapuliyur et al into the device of Yang et al in order to decrease the resistance of the gate.
With respect to claim 10, Thirupapuliyur et al (fig. 2) discloses wherein a bottommost surface of the silicide layer (122, pp [0023]) is vertically offset from a top surface of the lower conductive structure by a lateral segment of the conductive gate layer that contacts a top surface of the lower conductive structure (121).
With respect to claim 13, Thirupapuliyur et al (fig. 2) discloses wherein the conductive gate layer (156, pp [0026]) comprises a vertical segment under the lateral segment, wherein the lower conductive structure extends along sidewalls of the vertical segment, and wherein a height of the vertical segment is greater than a vertical distance between an upper surface of the lower conductive structure (152, pp [0023]) and an upper surface of the gate dielectric structure (107, 150, pp [0019]; [0022]).
With respect to claim 14, Thirupapuliyur et al (fig. 2) discloses wherein second opposing sidewalls of the conductive gate body layer (122, pp [0023]) are aligned with opposing sidewalls of the silicide layer (122, pp [0023]).
With respect to claim 15, Thirupapuliyur et al (fig. 2) discloses wherein a width of the silicide layer (122, pp [0023]) is equal to a width of the gate dielectric structure (112, pp [0022]).
Allowable Subject Matter
Claims 11-12 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to disclose wherein a height of the lateral segment is less than a height of the silicide layer, wherein the height of the silicide layer is less than a height of the lower conductive structure (claim 11); wherein the lower conductive structure comprises a plurality of metal layers, wherein a bottommost metal layer in the plurality of metal layers has a thickness less than a height of the lateral segment (claim 12); a dielectric structure on the semiconductor substrate, wherein the dielectric structure laterally surrounds the gate dielectric structure and the gate electrode, wherein a top surface of the dielectric structure is aligned with a top surface of the second gate layer, and wherein a distance between the top surface of the dielectric structure and the top surface of the conductive structure is greater than a height of the second gate layer; and a conductive via arranged on the second gate layer (claim 24).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V PHAM whose telephone number is (571)272-1715. The examiner can normally be reached M-F 8:30a.m-10:00p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached at 571-271-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HOAI V PHAM/Primary Examiner, Art Unit 2892