Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1-3 and 6-19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2023/0402518; hereinafter Park) in view of IM et al. (US 2019/0088657; hereinafter IM).
Regarding claim 1, Park, in fig. 2, discloses a memory device, comprising: a semiconductor substrate 110 having a trench 120T; a word line structure 120 disposed in a semiconductor substrate, wherein the word line structure 120 (fig. 6) comprises: a lower gate electrode layer 124a; an upper gate electrode layer 124b disposed over the lower gate electrode layer 124a, wherein a work function of the lower gate electrode layer 124a (metal) is different from a work function of the upper gate electrode layer 124b (polysilicon) ([0036]); a pair of spacers 122c disposed on opposite sides of the upper gate electrode layer 124b; and a gate dielectric layer 122a/122b surrounding the lower gate electrode layer 124a and the pair of spacers 122c; a first source/drain region 114A and a second source/drain region 114B disposed in the semiconductor substrate and at opposite sides of the word line structure 120; a bit line structure 130 disposed over and electrically connected to thefirst source/drain region 114A; and a capacitor CS1 disposed over and electrically connected to the second source/drain region 114B.
Park fails to disclose the thickness of the lower portion of the gate dielectric layer is greater than the thickness of the upper portion of the gate dielectric layer.
However, IM, in fig. 4, discloses the gate dielectric layer 210 is a single layer conformally formed on and in direct contact with a sidewall of the trench 120; wherein the gate dielectric layer 210 comprises: a lower portion 212 surrounding and in contacting with the lower gate electrode layer 220/230; and an upper portion 214 surrounding the upper gate electrode layer 240, wherein a thickness of the lower portion 212 of the gate dielectric layer 210 is greater than a thickness of the upper portion 214 of the gate dielectric layer 210. It would have been obvious to those having ordinary skill in the art at the time of invention to form a gate dielectric layer structure as taught by IM, so that the gate-induced drain leakage current (GIDL) can be mitigated at uncompromised turn-on performance and saturation current performance of the transistor, thus overcoming the problem of conflicting performance enhancement and GIDL mitigation.
Regarding claim 2, Park discloses wherein the work function of the lower gate electrode
layer 124a (metal) is higher than the work function of the upper gate electrode layer 124b
(polysilicon) ([0036]).
Regarding claim 3, Park discloses wherein the lower gate electrode layer 124a comprises
titanium nitride (TiN), and the upper gate electrode layer 124b comprises polysilicon ([0036]).
Regarding claim 6, Park discloses wherein the upper gate electrode layer 124b is
separated from the gate dielectric layer 122b by the pair of spacers 122c-1 (fig. 6).
Regarding claim 7, Park discloses wherein the lower gate electrode layer 124a is in direct
contact with the pair of spacers 122c-1 (fig. 6).
Regarding claim 8, Park discloses further comprising: a dielectric cap layer 142 disposed
over the semiconductor substrate, wherein a portion of the dielectric cap layer 142 extends into
the semiconductor substrate to cover the word line structure 120 (fig. 2).
Regarding claim 9, Park discloses wherein the dielectric cap layer 126/142 is in direct
contact with the upper gate electrode layer 124b (fig. 2).
Regarding claim 10, Park discloses wherein the dielectric cap layer 126/142 is in direct
contact with the pair of spacers 122c-1 (fig. 6).
Regarding claim 11, Park discloses further comprising: a lining layer 122c disposed
between the gate dielectric layer 122b and the dielectric cap layer 126/142, wherein the portion of the dielectric cap layer 126/142 is surrounded by the lining layer 122c and is extended through the lining layer 122c in order to direct contact the upper gate electrode layer 124b (fig. 3).
Regarding claim 12, Park discloses wherein the lining layer 122c is in direct contact with the pair of spacers 122c (fig. 3).
Regarding claim 13, Park discloses wherein the upper gate electrode layer 124b and the pair of spacers 122c are separated from the dielectric cap layer 126/142 by the lining layer 122c (fig. 3).
Regarding claim 14, Park discloses wherein the lining layer 122c extends over the semiconductor substrate, and a top surface of the gate dielectric layer 122a/122b is covered by the lining layer 122c (fig. 3).
Regarding claim 15, Park discloses further comprising: a bit line contact 132 disposed between the first source/drain region 114A and the bit line structure 134, wherein the bit line contact 132 is in direct contact with the lining layer 122c (fig. 2).
Regarding claim 16, Park discloses further comprising: a mask layer 144 disposed between the capacitor CS1 and the second source/drain region 114B of the semiconductor substrate, wherein the mask layer 144 is in direct contact with the lining layer 122c (fig. 2).
Regarding claim 17, Park discloses further comprising: a capacitor contact 150/152 disposed between and electrically connect the capacitor CS1 and the second source/drain region 114B of the semiconductor substrate, wherein the capacitor contact 150/152 penetrates through the mask layer 144 (fig. 2).
2. Claims 1, 2 and 6-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2017/0365608; hereinafter Lee) in view of IM et al. (US 2019/0088657; hereinafter IM).
Regarding claim 1, Lee, in fig. 2, discloses a memory device, comprising: a word line
structure 132/134 disposed in a semiconductor substrate, wherein the word line structure 132/134
comprises: a lower gate electrode layer 132; an upper gate electrode layer 134 (148) disposed
over the lower gate electrode layer 132, wherein a work function of the lower gate electrode
layer 132 is different from a work function of the upper gate electrode layer 134 (the work
function of the lower gate electrode layer 132 is higher than a work function of the upper gate
electrode layer 134 ([0056])); a pair of spacers 146 disposed on opposite sides of the upper gate
electrode layer 148; and a gate dielectric layer 120 surrounding the lower gate electrode layer
132 and the pair of spacers 146; a first source/drain region 109A and a second source/drain
region 109B disposed in the semiconductor substrate and at opposite sides of the word line
structure 132/134; a bit line structure 150 disposed over and electrically connected to the first
source/drain region 109A; and a capacitor 180 disposed over and electrically connected to the
second source/drain region 109B.
Lee fails to disclose the thickness of the lower portion of the gate dielectric layer is greater than the thickness of the upper portion of the gate dielectric layer.
However, IM, in fig. 4, discloses the gate dielectric layer 210 is a single layer conformally formed on and in direct contact with a sidewall of the trench 120; wherein the gate dielectric layer 210 comprises: a lower portion 212 surrounding and in contacting with the lower gate electrode layer 220/230; and an upper portion 214 surrounding the upper gate electrode layer 240, wherein a thickness of the lower portion 212 of the gate dielectric layer 210 is greater than a thickness of the upper portion 214 of the gate dielectric layer 210. It would have been obvious to those having ordinary skill in the art at the time of invention to form a gate dielectric layer structure as taught by IM, so that the gate-induced drain leakage current (GIDL) can be mitigated at uncompromised turn-on performance and saturation current performance of the transistor, thus overcoming the problem of conflicting performance enhancement and GIDL mitigation.
Regarding claim 2, Lee discloses wherein the work function of the lower gate electrode
layer 132 is higher than the work function of the upper gate electrode layer 134 ([0056]).
Regarding claim 6, Lee discloses wherein the upper gate electrode layer 148 is separated
from the gate dielectric layer 120 by the pair of spacers 146 (fig. 2).
Regarding claim 7, Lee discloses wherein the lower gate electrode layer 132 is in direct
contact with the pair of spacers 146 (fig. 2).
Regarding claim 8, Lee discloses further comprising: a dielectric cap layer 136 disposed
over the semiconductor substrate, wherein a portion of the dielectric cap layer 136 extends into
the semiconductor substrate to cover the word line structure 132/134 (fig. 2).
Regarding claim 9, Lee discloses wherein the dielectric cap layer 136 is in direct contact
with the upper gate electrode layer 148 (fig. 2).
Regarding claim 10, Lee discloses wherein the dielectric cap layer 136 is in direct contact
with the pair of spacers 146 (fig. 6).
Regarding claim 11, Lee discloses further comprising: a lining layer 149K disposed
between the gate dielectric layer 120 and the dielectric cap layer 136, wherein the portion of the dielectric cap layer 136 is surrounded by the lining layer 149K and is extended through the lining layer 149K in order to direct contact the upper gate electrode layer 148 (figs. 2 & 20B).
Regarding claim 12, Lee discloses wherein the lining layer 149K is in direct contact with
the pair of spacers 146 (fig. 20B).
Regarding claim 13, Lee discloses wherein the upper gate electrode layer 148 and the
pair of spacers 146 are separated from the dielectric cap layer 136 by the lining layer 149K (figs.
2 & 20B).
Regarding claim 14, Lee discloses wherein the lining layer 149K extends over the
semiconductor substrate, and a top surface of the gate dielectric layer 120 is covered by the
lining layer 149K (fig. 20B).
Regarding claim 15, Lee discloses further comprising: a bit line contact 152 disposed
between the first source/drain region 109A and the bit line structure 154/156, wherein the bit line
contact 152 is in direct contact with the lining layer 149K (figs. 2 & 20B).
Regarding claim 16, Lee discloses further comprising: a mask layer 170 disposed
between the capacitor 180 and the second source/drain region 109B of the semiconductor
substrate, wherein the mask layer 170 is in direct contact with the lining layer 149K (figs. 2 &
20B).
Regarding claim 17, Lee discloses further comprising: a capacitor contact 160 disposed
between and electrically connect the capacitor 180 and the second source/drain region 109B of
the semiconductor substrate, wherein the capacitor contact 160 penetrates through the mask layer 170 (fig. 2).
3. Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US
2023/0402518) in view of IM (US 2019/0088657); and further in view of Chou et al. (US 2022/0028867; hereinafter Chou).
Regarding claim 4, the combination of Park and IM fails to disclose a width of the lower gate electrode layer is greater than a width of the upper gate electrode layer.
However, Chou, in fig. 2f, discloses a width of the lower gate electrode layer 100 (below the line H1) is greater than a width of the upper gate electrode layer 100 (above the line H1). It would have been obvious to those having ordinary skill in the art at the time of invention to form a gate structure as taught by Chou, so that the current leakage between the word lines and the active areas can be mitigated. In particular, current leakage between the portions of the word lines in the trench structures and the active areas can be effectively mitigated.
Regarding claim 5, Chou discloses wherein the spacers 220 are surrounded by and in contact with the upper portion of the gate dielectric layer 210, wherein the spacers 220 and the upper gate electric layer 210 are in direct contact with a top surface of the lower gate electrode layer 100 (fig. 2f).
Response to Arguments
4. Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
5. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818
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