DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 17-20, and 31-33 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by ONOGAWA et al. (2025/0192058, hereinafter, Onogawa.)
In regard to claims 1, 17, and 31, in fig. 1, Onogawa discloses a semiconductor device 100 (para [0008]), comprising:
a semiconductor structure inherently having an active region 120 therein (para [0024]);
a gate pad 112 (para [0030]) on the semiconductor layer structure, the gate pad positioned to be closest to a first side of the active region;
a plurality of gate electrodes 45 (para [0027]); and
a metal gate runner 130 (para [0032]) that electrically connects the gate pad to at least some of the gate electrodes, the metal gate runner comprising an outer runner that extends around a portion of a periphery of the active region,
wherein, when the semiconductor device is viewed in plan view, the outer gate runner comprises a first outer segment that extends along at least a portion of the first side of the active region and a second outer segment that extends along at least a portion of a second side of the active region that connects to the first side, but the outer gate runner does not extend along a third side of the active region that is opposite the second side.
Regarding claim 2, wherein, when the semiconductor device is viewed in plan view, the outer gate runner does not extend along a portion of the first side of the active region that is in between the gate pad and the third side of the active region. Fig. 1.
Regarding claim 18, wherein the first side of the active region connects to the second side of the active region. Fig. 1.
Regarding claim 19, wherein the outer gate runner only includes a single outer segment that directly connects to the gate pad. Fig. 1.
Regarding claims 20 and 32-33, wherein the gate pad is positioned to be closest to the first side of the active region, and the outer gate runner does not extend along a third side and fourth side of the active region that is opposite the second side of the active region. Fig. 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5, 7-8, 10, 13-14, 28-29, 34, and 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Onogawa as applied to claim 1 above, and further in view of Lichtenwalmer et al. (US 2022/0149165, hereinafter, Lichtenwalmer.) And/Or KAKIMOTO (US 2018/0308757, hereinafter, Kakimoto.)
In regard to claims 4, 13, 28, and 34, Onogawa discloses all of the claimed limitations as mentioned above, except wherein the metal gate runner further comprises an inner gate runner that includes a plurality of inner segments that extend inwardly from the outer gate runner.
Lichtenwalmer, in figs. 2A and 4A, (or Kakimoto’s fig. 3)discloses an analogous semiconductor structure including a gate pad 106 (para [0077]), a gate runner, or buses, 236 (para [0100]). The runner further includes an inner gate runner that includes a plurality of inner segments that extend inwardly from the outer gate runner in order to provide additional electrical connection to the gate. It is common in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the filing date to recognize the structure as taught in order to take the advantage as mentioned.
Regarding claims 5 and 7, Lichtenwalmer and Kakimoto (fig. 3) further disclose wherein at least some of the inner segments extend at right angles from the second outer segment of the outer gate runner, and wherein the inner segments that extend from the second outer segment of the outer gate runner do not extend all the way to the third side of the active region. Fig. 2A.
Regarding claims 8, 10, and 37, the above combination discloses the dimensions of the elements except the exact value as currently claimed, a various number of values. However, the dimensions of the elements are not considered to be critical values, or otherwise disclosed. The values may be adjusted during a routine of the manufacturing to meet certain design criteria. It is common in the art.
Regarding claims 14 and 29, Lichtenwalmer (or Kakimoto’s fig. 3) wherein the first inner segment extends in parallel to the second outer segment. Fig. 4A.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN W HA/Primary Examiner, Art Unit 2814
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