DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Liaw (US Pat. 9,558,809).
Regarding claim 1, Fig. 2 of Liaw discloses a semiconductor structure, comprising:
a substrate [10];
a first Gate-All-Around (GAA) [Fig. 2, col. 3 lines 59-62, PD1] device comprising:
a first pair of source/drain [15N/115N] features disposed on the substrate [10], and
first vertically stacked channel layers [110N] connecting the first pair of source/drain [15N/115N] features; and
a second GAA device [PU1] comprising:
a second pair of source/drain [15P/115P] features disposed on the substrate [10],
and
second vertically stacked channel layers [110P] connecting the second pair of source/drain [15P/115P] features,
wherein one channel layer of the first vertically stacked channel layers [110N] has a first width [short side] and a first vertical thickness [long side],
wherein one channel layer of the second vertically stacked channel layers [110P] has a second width [short side of 110P] and a second vertical thickness [long side of 110P], and
wherein a first ratio of the first width to the first vertical thickness [short side/long side of 110N] is greater [as discloses in col. 4 lines 41-66, the thickness (long side) of channels 110N and 110P are the same. However, the width (short side) of channel 110N is 20% wider than the width (short side) of channel 110P. Therefore, the ratio of first width and first thickness is larger than the ratio of second width and second thickness] than a second ratio of the second width to the second vertical thickness [short side/long side of 110N].
Regarding claim 2, Fig. 2 of Liaw discloses wherein the substrate comprises a first well [10N] and a second well [10P] of different types, wherein the first pair of source/drain [15N/115N] features are disposed on the first well [10N], and wherein the second pair of source/drain [15P/115P] features are disposed on the second well [15P].
Regarding claim 3, col. 3 lines 41-61 Liaw discloses the second ratio (5/10) and the first ration is 20% larger, but does not specifically disclose wherein the first ratio is between about 2 and about 10, and the second ratio is between about 0.9 and about 2. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust the first ratio between 2 and 10, and second ration between .9 and 2, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. MPEP 2144.05; In re Aller, 105 USPQ 233.
Regarding claim 4, Fig. 2 of Liaw discloses wherein the first GAA device further comprises a first metal gate structure [130N] wrapping around each of the first vertically stacked channel layers [110N], wherein the second GAA device further comprises a second metal gate structure [130P] wrapping around each of the second vertically stacked channel layers [110P], and wherein the first metal gate structure and the second metal gate structure are separated by a gate isolation structure [120N, 120P].
Regarding claim 5, Fig. 2 of Liaw discloses a metal gate structure [130N, 130P] wrapping around each of the first vertically stacked channel layers [110N] and the second vertically stacked channel [110P] layers.
Regarding claim 6, Fig. 1B and Fig. 2 of Liaw discloses wherein the substrate further comprises a third well of a same type as the first well [Fig. 2 shows an example of PD1 and PU1. However, as shows in Fig. 1B, the memory cells also comprises PD2 and PU2, which are identical to PD1 and PU2 respectively. Therefore, the third well is identical to 10N, but for PD2], wherein the semiconductor structure further comprises a third GAA device comprising: a third pair of source/drain [similar to 15N/115N] features disposed on the third well [similar to 15N], and third vertically stacked channel layers [similar to 110N] connecting the third pair of source/drain [15N/115N] features, wherein one channel layer of the third vertically stacked channel layers has a third width and a third vertical thickness [similar to first ratio], and wherein a third ratio of the third width to the third vertical thickness is greater than the second ratio [similar to first ratio being greater than second ratio].
Regarding claims 7 and 12, Fig. 1B and Fig. 2 of Liaw discloses a third GAA device [similar to second GAA device, PU1] comprising: a third pair of source/drain [similar to 15P/115P] features disposed on the second well [10P], and third vertically stacked channel layers [110P] connecting the third pair of source/drain [15P/115P] features, wherein one channel layer of the third vertically stacked channel layers has a third width and a third vertical thickness [similar to second width and thickness belong to PU1], and wherein a third ratio of the third width [similar to second ratio] to the third vertical thickness is less than the first ratio.
Regarding claim 8, Fig. 2 of Liaw discloses a semiconductor structure, comprising:
a first region [10N] and a second region [10P] over a substrate [10];
a first transistor [PD1] on the first region [10N] and comprising vertically stacked multiple first channels [110N]; and
a second transistor [PU1] on the second region [10P] and comprising vertically stacked multiple second channels [110P],
wherein one channel of the first channels [110N] has a first width [short side] and a first thickness [long side], and one channel of the second channels [110P] has a second width [short side of 110P] and a second thickness [long side of 110P], and wherein a first ratio of the first width to the first thickness is greater [as discloses in col. 4 lines 41-66, the thickness (long side) of channels 110N and 110P are the same. However, the width (short side) of channel 110N is 20% wider than the width (short side) of channel 110P. Therefore, the ratio of first width and first thickness is larger than the ratio of second width and second thickness] than a second ratio of the second width to the second thickness.
Regarding claims 9 and 16, Fig. 1B and Fig. 2 of Liaw discloses wherein the first transistor is of a first type [PD1, NMOS], and the second transistor [PU1, PMOS] is of a second type different from the first type
Regarding claims 10, 11, and 17, Fig. 1B and Fig. 2 of Liaw discloses a third transistor [PU2] on the second region [10P] and comprising vertically stacked multiple third channels [similar to 110P], wherein the third transistor is of the first type [PU2 is PMOS], wherein one channel of the third channels has a third width and a third thickness [similar to PU1], and wherein a third ratio [similar to second ratio] of the third width to the third thickness is less than the first ratio.
Regarding claims 13 and 18, Fig. 1B and Fig. 2 of Liaw discloses wherein one channel of the fourth channels [similar to 110P of PU2, which is identical to 110P of PU1] has a fourth width and a fourth thickness [similar to 110P], and wherein a fourth ratio of the fourth width to the fourth thickness is about the same as the third ratio [which is also similar to second ratio].
Regarding claim 14, Fig. 1B and Fig. 2 of Liaw discloses a third transistor [PD2] on the first region [10N], wherein the third transistor comprises vertically stacked multiple third channels [similar to 110N], wherein one channel of the third channels has a third width and a third thickness [similar to first width and thickness], and wherein a third ratio of the third width to the third thickness is about the same as the first ratio [since PD1 and PD2 are identical transistors, third ratio is same as first ratio].
Regarding claim 15, Fig. 1B and Fig. 2 of Liaw discloses a third transistor [PD2, which is identical to PD1] on the first region [10N], wherein the third transistor comprises vertically stacked multiple third channels [identical to 110N], wherein one channel of the third channels has a third width and a third thickness [similar to first width and thickness of PD1], and wherein a third ratio of the third width to the third thickness is about the same as the first ratio [same as first ratio because PD1 and PD2 are identical].
Regarding claim 15, Fig. 2 of Liaw discloses a semiconductor structure, comprising:
a first transistor region [10N] comprising a first transistor [PD1] and a second transistor region [10P] comprising a second transistor [PU1], wherein the first transistor comprises a plurality of first nanostructures [110N, col. 4 lines 41 to 61] stacked vertically one over another, and wherein the second transistor [PU1] comprises a plurality of second nanostructures [110P, col. 4 lines 41 to 61] stacked vertically one over another;
a first metal gate structure [130N] wrapping around the plurality of first nanostructures [110N];
a second metal gate structure [130P] wrapping around the plurality of second nanostructures [110P]; and
an isolation feature [120P] disposed between the first transistor region and the second transistor region,
wherein one nanostructure [110N] of the plurality of first nanostructures has a first width [short side] and a first thickness [long side],
wherein one nanostructure of the plurality of second nanostructures [110P] has a second width [short side] and a second thickness [long side], and
wherein a first ratio of the first width to the first thickness is greater [as discloses in col. 4 lines 41-66, the thickness (long side) of channels 110N and 110P are the same. However, the width (short side) of channel 110N is 20% wider than the width (short side) of channel 110P. Therefore, the ratio of first width and first thickness is larger than the ratio of second width and second thickness] than a second ratio of the second width to the second thickness.
Regarding claim 19, Fig. 2 of Liaw discloses wherein the second metal gate structure [130P] further wraps around the plurality of the third nanostructures [110P].
Regarding claim 20, Fig. 2 of Liaw discloses wherein the second transistor region [10N] further comprises a third transistor [PD2, similar to PD1], wherein the third transistor comprises a plurality of third nanostructures [similar to 110N] stacked vertically one over another, wherein the third transistor is of the first type [NMOS], wherein one nanostructure of the plurality of third nanostructures has a third width and a third thickness [similar to first width and thickness because PD2 is identical to PD1], and wherein a third ratio [similar to first ratio] of the third width to the third thickness is greater than the second ratio [ratio of short/long sides of 110P].
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825