DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 11 and 17.
b. Pending: 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-6, 10, 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fick PG PUB 20190326921 in view of Chen PG PUB 20190102170 (hereinafter Chen).
Regarding independent claim 1, Fick teaches a system, comprising: a global generator configured to generate a plurality of global signals (Fick teaches a global reference signal source, including a binary-weighted global reference signal source, that generates plural reference signals, [0091], “…a system 700 for implementing mixed-signal computing for computationally-intensive programs and/or applications includes a global reference generator 710…”); and a plurality of compute-in-memory (CIM) input or output (I/O) circuits (720 in figure 7) coupled to the global generator, wherein each of the plurality of CIM IO circuits (720 in figure 7) is configured to generate, in response to the plurality of global signals, a plurality of output signals ([0100], “…local accumulators 720 may function to generate an analog output…plurality of local accumulators 720 comprise a plurality of local digital-to-analog converters (LDACs) that may function to generate the analog output over several clock cycles using the global reference signals from the global reference generator 710…”) according to a corresponding one in a plurality of local signals.
But Fick does not teach the output signals are generated according to a multiply-and-accumulate signal from a memory array.
Chen teaches compute-in-memory device in which memory cells store weights and directly perform multiple-and-accumulate operations. Chen teaches in [0015], “…processing elements of a CIM circuit may compute a MAC value via use of current summing for one or more columns of bitcells of an array included in the CIM circuit…”
Fick teaches a globally driven mixed-signal computing architecture with a centralized generator distributing reference signals to multiple local compute circuits. Chen teaches compute-in-memory MAC operations using memory arrays. It would have been obvious to one of ordinary skill in the art to incorporate Chen’s CIM MAC circuitry into Fick’s local accumulators in order to perform memory based weighted-sum computation under centralized global control, yielding predictable improvement in scalability, efficiency, consistent with the design goals expressed stated in both references.
Regarding claim 2, the combination of Fick and Chen teaches the system of claim 1, wherein each of the plurality of CIM I/O circuits comprises: a local generator (“local signal source” in claim 1 of Fick,”… binary reference signal source that sources one or more signals to an array of local signal sources, wherein a distinct one local signal source of the array of local signal sources is arranged in electrical communication with the pair of electrical conduits…”), comprising: a plurality of reference circuits configured to generate a plurality of reference signals sequentially to a node in response to the plurality of global signals (claim 14 of Fick, “…the binary reference signal source executes a binary search algorithm such that at each step of the binary search algorithm, the binary reference signal source sets a binary-weighted value with which each of the array of local signal sources to adjust a respective local state of each of the array of local signal sources…”, thus Fick teaches sequential reference signal generation responsive to global (binary reference) signals); and a reference signal generator coupled to the plurality of reference circuits at the node ([0078] of Chen, “…memory circuit may also an operational amplifier having a first input coupled with the bitline and a second input coupled with a reference voltage… an output of the operational amplifier coupled to a resistance device…”, thus Chen teaches a node at which reference signals and memory derived signals are combined and sensed), and configured to generate one in the plurality of local signals in response to the plurality of reference signals (Fick teaches generating local signals based on reference values determined during sequential reference process).
Regarding claim 32, the combination of Fick and Chen teaches the system of claim 2, wherein the reference signal generator comprises: a first transistor having a source/drain terminal coupled to a ground and further having a drain/source terminal and a gate terminal that are coupled to the node; and a second transistor having a source/drain terminal coupled to the ground and a gate terminal coupled to the node and further having a drain/source terminal configured to output the one in the plurality of local signals (Chen teaches transistor-level CIM circuitry, including MOFETS couples to ground and supply, used in sensing and reference paths. [0080] of Chen, “… 6T SRAM bitcells may include a first and second cross-coupled inventors that may separately include a P-channel MOSFET and an N-channel MOSFET. The P-channel MOSFETs may be coupled to a supply voltage (VDD) and the N-channel MOSFETs coupled to ground…”, Fick teaches that local signal sources output local signals to corresponding electrical conduits, and Chen supplied the transistor-level implementation for generating such outputs, together, Fick provides the functional role (outputting local signals) and Chen provides the structure transistor implementation).
Regarding claim 4, the combination of Fick and Chen teaches the system of claim 1, wherein each of the plurality of CIM I/O circuits comprises: a local generator, comprising: a first reference circuit configured to generate a first reference signal at a node, in response to a first global signal of the plurality of global signals in a first cycle; a second reference circuit configured to generate, in response to a second global signal in the plurality of global signals and a first output signal in the plurality of output signals, a second reference signal at the node in a second cycle; and a third reference circuit coupled to the second reference circuit, and configured to generate, in response to a third global signal in the plurality of global signals, a third reference signal at the node in a third cycle (Fick teaches in claim 14 multi-cycle reference generation controlled by global signals, including successive reference values generated during iterative sensing cycles).
Regarding claim 5, the combination of Fick and Chen teaches the system of claim 4, wherein when a value of a reference signal at the node is greater than a value of the multiply-and-accumulate signal in the first cycle, the second reference circuit is activated to generate a positive-phased reference signal as the second reference signal to the node (Fick teaches comparison-based control where the outcome of a comparison determines the next reference adjustment direction (se claim 14, “…the binary reference signal source executes a binary search algorithm such that at each step of the binary search algorithm, the binary reference signal source sets a binary-weighted value with which each of the array of local signal sources to adjust a respective local state of each of the array of local signal sources”, in such algorithms, when the reference exceeds the sensed value, the next step adjusts the reference in a corresponding direction).
Regarding claim 6, the combination of Fick and Chen teaches the system of claim 5, wherein when the value of the reference signal is less than the value of the multiply-and-accumulate signal in the second cycle, the third reference circuit is activated to generate a negative-phased reference signal as the third reference signal to the node (Fick teaches bidirectional reference adjustment based on comparison results).
Regarding claim 10, the combination of Fick and Chen teaches the system of claim 1, wherein each of the plurality of CIM I/O circuits comprises: a sense amplifier (150 in figure 1 of Fick, “operational amplifier” in [0078] of Chen) configured to generate the plurality of output signals(DOUT) in response to the multiply-and-accumulate signal and one of the plurality of local signals ([0087] of Chen, “…CIM circuit may also include processing circuitry to include an analog processor to sense an analog voltage output from the operational amplifier and convert the analog voltage to a digital value to compute a MAC value…”)
Regarding independent claim 17, the combination of Fick and Chen teaches a method, comprising: activating, in response to an enable signal, a sense amplifier to generate a corresponding one of a plurality of output signals in a corresponding one in a plurality of sensing cycles (Chen in [0078] teaches activation of sensing circuitry to generate outputs from a MAC signals); and adjusting a reference signal according to the plurality of output signals and a plurality of global signals in the plurality of sensing cycles (Fick teaches in claim 14 an iterative, cycle-by-cycle adjustment of reference values, “…the binary reference signal source executes a binary search algorithm such that at each step of the binary search algorithm, the binary reference signal source sets a binary-weighted value with which each of the array of local signal sources to adjust a respective local state of each of the array of local signal sources…the binary reference source executes one of a least significant bit search algorithm, a non-binary search algorithm, a logarithmic search algorithm…”), wherein activating the sense amplifier to generate the corresponding one of the plurality of output signals comprises: comparing the reference signal with a multiply-and-accumulate signal to generate the corresponding one of the plurality of output signals (Chen teaches comparison of a reference voltage with a MAC derived signal, [0078] of Chen, “…an operational amplifier having a first input coupled with the bitline and a second input coupled with a reference voltage…”)
Regarding claim 18, the combination of Fick and Chen teaches the method of claim 17, wherein adjusting the reference signal comprises: pulling down the reference signal by a plurality of N type transistors mirroring the plurality of global signals responsive to global signals (Fick teaches transistor-based control of signal levels, claim 20 of Fick, “…distinct one local signal source of the array of local signal sources is arranged in electrical communication with the pair of electrical signal paths…”, Under BRI, sourcing a signal in response to a global/binary reference include pull-down behavior using transistor devices).
Regarding claim 19, the combination of Fick and Chen teaches the method of claim 17, wherein adjusting the reference signal comprises: pulling up the reference signal by at least one P type transistor being turned on in response to one of the plurality of global signals (Fick teaches reference signals being driven in response to a global/binary reference signals, Chen teaches PMOS structure used in reference and sensing paths, using p-type device to pull a node toward a supply voltage in response to a control/reference signal is an obvious implementation of the reference adjustment of Fick).
Regarding claim 20, the combination of Fick and Chen teaches the method of claim 17, wherein adjusting the reference signal comprises: transmitting one of the plurality of global signals in response to one of the plurality of output signals in each of the plurality of sensing cycles (Fick teaches transmitting different reference signals during successive steps).
Allowable Subject Matter
Claims 11-16 are allowed.
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior arts to the present invention are Fick PG PUB 20190326921 in view of Chen PG PUB 20190102170 (hereinafter Chen).
Fick discloses a mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.
Chen discloses a compute-in-memory (CIM) circuit that enables a multiply-accumulate (MAC) operation based on a current-sensing readout technique. An operational amplifier coupled with a bitline of a column of bitcells included in a memory array of the CIM circuit to cause the bitcells to act like ideal current sources for use in determining an analog voltage value outputted from the operational amplifier for given states stored in the bitcells and for given input activations for the bitcells. The analog voltage value sensed by processing circuitry of the CIM circuit and converted to a digital value to compute a multiply-accumulate (MAC) value.
Regarding claim 7, the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the third reference circuit mirrors the third global signal to generate the third reference signal.
Regarding claim 8 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the first reference circuit comprises: a first switch configured to receive the first global signal; and a first P-type transistor having a gate terminal coupled to the first switch and a drain/source terminal coupled to the node.
Regarding independent claim 11 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: at least one local generator coupled to a memory array, comprising: a current mirror; a sense amplifier having a first input coupled to the current mirror and a second input coupled to a multiply-and-accumulate circuit.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824