DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/06 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "218" and "220" in Fig. 11B have both been used to designate the isolation structure. It appears that 218 is intended to reference the fin spacer layer.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-8, 10-11 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al. (PG Pub. No. US 2018/0323312A1, Van Dal herein after) in view of Hsu et al. (PG Pub No. US 2020/0135551A1, Hsu hereinafter).
Regarding claim 1, Van Dal teaches a semiconductor device (Fig. 33B), comprising:
a fin-shaped structure (P[0067]; protruded portions of the fin 602a) extending lengthwise along a direction (Annotated Fig. 33B, 602a extends along direction Y);
an isolation feature (P[0068]: isolation structure 604) adjacent the fin-shaped structure (Fig. 33B, 604 is adjacent to 602a);
a source/drain feature (P[0083]: source and drain regions 716 and lateral extension of 614) disposed over the fin-shape structure (Fig. 33B, 716 is over 602a);
an isolation structure (P[0070]: spacers 712) disposed over the isolation feature (Fig. 33B, 712 is over 604);
and a gate extension structure (P[0079-0080]: composited structure of dielectric layer 730, work function metal layer 740 and/or gate electrode 750) sandwiched between the source/drain feature and the isolation structure (Fig. 33B, 730/740/750 is sandwiched between 716 and 712),
wherein the gate extension structure is disposed over and in contact with the fin-shaped structure and the isolation feature (Fig. 33B, 730/740/750 is in contact with 602a and 604).
However, Van Dal does not teach a silicon liner sandwiched between the fin-shaped structure and the isolation feature along the direction; and the gate extension structure is disposed over and in contact with the silicon liner.
Hsu teaches a semiconductor device (¶ 0045 & figs. 16A-16B: 250) including a silicon liner (P[0017]: Si liner layer 210) sandwiched between a fin-shaped structure (P[0013]: semiconductor fins 201, similar to 602a of Van Dal) and an isolation feature (P[0025]: trench isolations 214, similar to 604 of Van Dal) along at least one direction (Fig. 16A, 210 is sandwiched between 201 and 214 in a fin-extending direction).
Since Van Dal and Hsu are in the same field of FET, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add a silicon liner layer adjacent to the trench isolation. This silicon liner layer would remove the water and improve the quality of the trench isolation, as suggested by Hsu (P[0023]: “the second liner layer 210 plays an important role for removing the water and improving the quality of the oxide layer 212”).
Furthermore, the semiconductor device of Van Dal as modified with the silicon liner of Hsu would include the feature of the gate extension structure contacting the fin-shaped structure, the silicon liner and the isolation feature. The gate extension structure is disposed over and in contact with the fin-shaped structure, the silicon liner, and the isolation feature (See annotated Fig. 33b, 730/740/750 is in contact with 602a, 604 and modified silicon liner).
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Regarding claim 2, Van Dal in view of Hsu teaches the semiconductor device of claim 1, wherein the gate extension structure comprises a work function layer (Van Dal P[0080]: work function metal layer 740) and a metal fill layer (Van Dal P[0080]: gate electrode 750).
Regarding claim 3, Van Dal in view of Hsu teaches the semiconductor device of claim 2, wherein the work function layer comprises titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). (Van Dal P[0060]: “The work function metal layer 340 may include materials such as TiN, TiAl, or TiAlC”; 340 is the same as 740 in Fig. 33B).
Regarding claim 4, Van Dal in view of Hsu teaches the semiconductor device of claim 2, wherein the metal fill layer comprises aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), or copper (Cu). (Van Dal P[0060]: “The gate electrode 350 may include material such as Al, W, Co, or Cu”; 350 is the same as 750 in Fig. 33B).
Regarding claim 5, Van Dal in view of Hsu teaches the semiconductor device of claim 1, further comprising:
a plurality of inner spacer Van Dal features (Van Dal P[0066]: sacrificial layer 612) disposed on a first sidewall of the source/drain feature (Fig. 33B, 612 are at the left side wall of 716), wherein the gate extension structure wraps over and is in contact with the plurality of inner spacer features (Van Dal, fig. 3B: 730/740/750 wraps over and contacts at least a corner region of 612).
Regarding claim 7, Van Dal in view of Hsu teaches the semiconductor device of claim 5, further comprising: a plurality of channel members (Van Dal, P[0066] channel region 614) disposed over the fin-shaped structure, wherein end surfaces of the plurality of channel members are in contact with a second sidewall of the source/drain feature. (Van Dal, Fig. 33B, 614 are on 602a and the end of 614 contacts the sidewall of 716).
Regarding claim 8, Van Dal in view of Hsu teaches the semiconductor device of claim 7, wherein the source/drain feature is sandwiched between the plurality of channel members and the gate extension structure. (Van Dal, Fig. 33B, source/drain 716 is sandwiched between channel 714 and gate extension 730/740/750).
Regarding claim 10, Van Dal teaches a semiconductor device (Fig. 33B), comprising:
a fin-shaped structure (P[0067]; protruded portions of the fin 602a) extending lengthwise along a direction (Annotated Fig. 33B, 602a extends along direction Y);
an isolation feature (P[0068]: isolation structure 604) adjacent the fin-shaped structure (Fig. 33B, 604 is adjacent to 602a);
a source/drain feature (P[0083]: source and drain regions 716 and lateral extension of 614) disposed over the fin-shape structure (Fig. 33B, 716/614 is over 602a); and
a gate extension structure (P[0079-0080]: composited structure of dielectric layer 730, work function metal layer 740 and/or gate electrode 750) disposed over and in contact with the fin-shaped structure and the isolation feature (Fig. 33B, 730/740/750 is in contact with 602a and 604);
a plurality of nanostructures (P[0066]: nanowires 614) disposed over the fin-shaped structure (Fig. 33B, 614 are on 602a); and
a gate structure (P[0079]: 730/740/750) wrapping around each of the plurality of nanostructures (Fig. 33B, 730 is wrapping around 614), wherein the source/drain feature is sandwiched between the gate structure and the gate extension structure (see annotated Fig. 33B, 716 is sandwiched between gate structure and gate extension),
wherein the source/drain feature is sandwiched between the gate structure and the gate extension structure (fig. 33B: 716/614 sandwiched between 730/740/750 in the channel region, and 730/740/750 in the source/drain region.
Van Dal does not teach a silicon liner sandwiched between the fin-shaped structure and the isolation feature along the direction; and the gate extension structure is disposed over and in contact with the silicon liner.
Hsu teaches a semiconductor device (¶ 0045 & figs. 16A-16B: 250) including a silicon liner (P[0017]: Si liner layer 210) sandwiched between a fin-shaped structure (P[0013]: semiconductor fins 201, similar to 602a of Van Dal) and an isolation feature (P[0025]: trench isolations 214, similar to 604 of Van Dal) along at least one direction (Fig. 16A, 210 is sandwiched between 201 and 214 in a fin-extending direction).
Since Van Dal and Hsu are in the same field of FET, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add a silicon liner layer adjacent to the trench isolation. This silicon liner layer would remove the water and improve the quality of the trench isolation, as suggested by Hsu (P[0023]: “the second liner layer 210 plays an important role for removing the water and improving the quality of the oxide layer 212”).
Furthermore, the semiconductor device of Van Dal as modified with the silicon liner of Hsu would include the feature of the gate extension structure contacting the fin-shaped structure, the silicon liner and the isolation feature. The gate extension structure is disposed over and in contact with the fin-shaped structure, the silicon liner, and the isolation feature (See annotated Fig. 33b, 730/740/750 is in contact with 602a, 604 and modified silicon liner).
Regarding claim 11, Van Dal in view of Hsu teaches the semiconductor device of claim 10, wherein the source/drain feature extends into the fin-shaped structure (Fig. 33B, 714 extends into 602a).
Regarding claim 14, Van Dal in view of Hsu teaches the semiconductor device of claim 10, wherein the gate structure comprises a gate dielectric layer (Van Dal: [0080], high-K dielectric layer 730), a work function layer over the gate dielectric layer (Fig. 33B, work function layer 740 is over 730), and a metal fill layer over the work function layer (Fig. 33B, metal fill 750 is over 740), wherein the gate extension structure comprises the work function layer (annotated Fig. 33B, 740 in gate extension region) and the metal fill layer (annotated Fig. 33B, 750 in gate extension region).
Regarding claim 15, Van Dal in view of Hsu teaches the semiconductor device of claim 14, wherein the work function layer of the gate extension structure directly contacts the source/drain feature (Van Dal, fig. 33B: 730 directly contacts projection of 614 extending from 716), wherein the metal fill layer of the gate extension structure is spaced apart from the source/drain feature by the work function layer (Van Dal, fig. 33B: 750 spaced apart from 614/716 by 730).
Regarding claim 16, Van Dal in view of Hsu teaches the semiconductor device of claim 10, further comprising:
a plurality of inner spacer features (Van Dal, ¶ 0066: features 612 formed in an inner space region) disposed on a sidewall of the source/drain feature (Van Dal, fig. 33B: 612 formed on a sidewall of 614/716), wherein the gate extension structure wraps over and is in contact with the plurality of inner spacer features (Van Dal, fig. 33B: 730/740/750 wraps over and contacts upper corner of 612).
Regarding claim 10, Van Dal teaches a semiconductor device (Fig. 33B), comprising:
a fin-shaped structure (P[0067]; protruded portions of the fin 602a) extending lengthwise along a direction (Annotated Fig. 33B, 602a extends along direction Y);
an isolation feature (P[0068]: isolation structure 604) adjacent the fin-shaped structure (Fig. 33B, 604 is adjacent to 602a);
a source/drain feature (P[0083]: source and drain regions 716 and lateral extension of 614) disposed over the fin-shape structure (Fig. 33B, 716/614 is over 602a); and
a gate extension structure (P[0079-0080]: composited structure of dielectric layer 730, work function metal layer 740 and/or gate electrode 750) disposed over and in contact with the fin-shaped structure and the isolation feature (Fig. 33B, 730/740/750 is in contact with 602a and 604); and
a gate structure (Van Dal, P[0080]: composited structure of 730/740/750) disposed over the fin-shaped structure and adjacent the source/drain feature (Van Dal, Fig. 33B, at gate region, 730/740/750 is over fin-shaped structure 602a and adjacent to source/drain 716),
wherein the source/drain feature is sandwiched between the gate structure and the gate extension structure (see annotated Fig. 33B, 716 is sandwiched between gate structure and gate extension),
wherein the source/drain feature is sandwiched between the gate structure and the gate extension structure (fig. 33B: 716/614 sandwiched between 730/740/750 in the channel region, and 730/740/750 in the source/drain region.
Van Dal does not teach a silicon liner sandwiched between the fin-shaped structure and the isolation feature along the direction; and the gate extension structure is disposed over and in contact with the silicon liner.
Hsu teaches a semiconductor device (¶ 0045 & figs. 16A-16B: 250) including a silicon liner (P[0017]: Si liner layer 210) sandwiched between a fin-shaped structure (P[0013]: semiconductor fins 201, similar to 602a of Van Dal) and an isolation feature (P[0025]: trench isolations 214, similar to 604 of Van Dal) along at least one direction (Fig. 16A, 210 is sandwiched between 201 and 214 in a fin-extending direction).
Since Van Dal and Hsu are in the same field of FET, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add a silicon liner layer adjacent to the trench isolation. This silicon liner layer would remove the water and improve the quality of the trench isolation, as suggested by Hsu (P[0023]: “the second liner layer 210 plays an important role for removing the water and improving the quality of the oxide layer 212”).
Furthermore, the semiconductor device of Van Dal as modified with the silicon liner of Hsu would include the feature of the gate extension structure contacting the fin-shaped structure, the silicon liner and the isolation feature. The gate extension structure is disposed over and in contact with the fin-shaped structure, the silicon liner, and the isolation feature (See annotated Fig. 33b, 730/740/750 is in contact with 602a, 604 and modified silicon liner).
Regarding claim 18, Van Dal in view of Hsu teaches the semiconductor structure of claim 17, further comprising: an isolation structure disposed over the isolation feature (Van Dal, Fig. 33B, 712 is on 604), wherein the gate extension structure is sandwiched between the source/drain feature and the isolation structure along the direction (Van Dal, Fig. 33B, gate extension is between 712 and source/drain 716).
Regarding claim 19, Van Dal in view of Hsu teaches the semiconductor structure of claim 17, wherein the gate extension structure comprises a work function layer (Van Dal, P[0080]: work function layer 740) and a metal fill layer (Van Dal, P[0080], gate electrode 750).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al. in view of Hsu as applied to claim 5 above, and further in view of Chao et al. (PG Pub. No. US 2018/0047835 A1).
Regarding claim 6, Van Dal in view of Hsu teaches the semiconductor device of claim 5, comprising a plurality of inner spacer features (Van Dal,612). Van Dal in view of Hsu teaches the inner spacers comprise sacrificial material (Van Dal, ¶ 0066).
Van Dal in view of Hsu does not teach wherein the plurality of inner spacer features comprise silicon nitride, silicon oxycarbonitride, silicon carbonitride, silicon oxide, silicon oxycarbide, silicon carbide, or silicon oxynitride.
Chao teaches a semiconductor device (fig. 7 among others) including inner spacers (¶ 0051: 135, formed by replacing portions of sacrificial semiconductor layers 122, similar to 612 of Van Dal), wherein the inner spacers comprise at least one of silicon oxide, silicon nitride, silicon oxynitride (¶¶ 0048, 0051).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the inner spacers of Van Dal with the material of Chao, as a means to provide electrical isolation between the gate and source/drain region, minimizing parasitic effects such as gate capacitance.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al. in view of Hsu as applied to claim 1 above, and further in view of Deng et al. (PG Pub. No. US 2017/0141111 A1).
Regarding claim 9, Van Dal in view of Hsu teaches the semiconductor device of claim 1, comprising an isolation structure (Van Dal, 712) including a dielectric feature (Van Dal, ¶ 0070).
Van Dal in view of Hsu does not teach wherein the isolation structure comprises:
a fin spacer layer and the dielectric feature disposed over the fin spacer layer,
wherein the dielectric feature is spaced apart from the isolation feature by the fin spacer layer.
Deng teaches semiconductor device (fig. 3) including an isolation structure (¶ 0040) comprising a fin spacer layer (¶¶ 0040-0041: 200a) and a dielectric feature (¶¶ 0040-0041: 200b) disposed over the fin spacer layer (fig. 3: 200b disposed over 200a),
wherein the dielectric feature is spaced apart from an isolation feature (¶ 0013: 104, similar to 604 of Van Dal) by the fin spacer layer (fig. 3: 200b spaced apart from 104 by 200a).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the isolation structure of Van Dal in view of Hsu with a fin spacer layer, as a means to improve etch resistance and/or minimize erosion of the isolation feature while performing addition processes, such as removing 310 of Van Dal.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al. in view of Hsu as applied to claim 10 above, and further in view of Kwon et al. (PG Pub No. US 2018/0301564A1, Kwon herein after).
Regarding claim 12, Van Dal in view of Hsu teaches the semiconductor device of claim 10 (see annotated fig. above).
However, Van Dal in view of Hsu does not teach a bottom surface of the source/drain feature spaced apart from the fin-shaped structure by a bottom dielectric feature and a void.
Kwon teaches a semiconductor device (figs. 2A-2B) comprising a bottom surface of a source/drain feature (P[0036]: source/drain regions SD, which include bottom surfaces) is spaced apart from a fin-shaped structure (P[0029] & fig. 2B: bottom of SD spaced apart from fin shape protruding AP) by a bottom dielectric feature (P[0075]: growth prevention region 148a, including dielectric material such as silicon nitride) and a void (P[0038]: air gap AG. Figs.2A-2B, SD is apart from AP by AG and 148a).
Since Van Dal, Hsu and Kwon are in field of FET, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add the air space and dielectric between source/drain and substrate. The air space and the dielectric layers prevents the current leakage between the source/drain and the substrate, as suggested by Kwon (P[0039]: “Thus, due to the presence of these air gaps AG, the bottom surfaces of the source/drain regions SD do not contact the substrate 100 thereby preventing or minimizing a current leakage between the source/drain regions SD and the substrate 100”).
Regarding claim 13, Van Dal in view of Hsu and Kwon teaches the semiconductor device of claim 12, wherein the void is disposed between the bottom dielectric feature and the source/drain feature (Kwon, Fig. 15A, AG is between 148a and SD).
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Van Dal teaches a metal fill layer is spaced apart from a fin-shaped structure and an isolation feature by a work function layer (Van Dal, fig. 33B: 750 spaced apart from 602a, and 604 by 740). Hsu teaches a silicon liner sandwiched between a fin-shaped structure and an isolation feature (figs. 16A-16B).
However, neither Van Dal nor Hsu, alone or in combination, teaches a work function layer in contact with a fin-shaped structure, a silicon liner, and an isolation feature as required by claim 20.
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818
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