DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 08/10/2026 is acknowledged.
Claims 1-10 are canceled pursuant to applicant’s amendment. Election was made without traverse in the reply filed on 08/10/2026. New claims 21-30 are examined as part of Group II.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Structure and Method for Forming Guarded Through-Substrate Vias of Different Sizes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 11, 18 and 21, the claimed language states that a second TSV is formed within a first structure. The drawings depict this occurring within part number 20B, while all previous limitations indicate part number 20B is a second structure and part number 20A is the first structure. No drawings depict the second TSV being formed within the first structure when properly following the claim. Correction is required.
Regarding claim 16, the claimed language requires a second surface of a third structure to be bonded to an interposer while the drawings instead depict a second surface of a first structure being bonded to the interposer. Correction is required.
Regarding claim 27, the limitation of a TSV having varying widths is not supported in the drawings. Correction or clarification on where this limitation is depicted is required.
Claims 12-15, 17, 19-20, 22-26 and 28-30 are rejected for depending from previously rejected claims 11, 18 and 21.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jeon et al. (US-20250038149-A1 – hereinafter Jeon).
Regarding claim 18, Jeon teaches a method, comprising:
forming a first structure (Fig.5 100; ¶0031), wherein forming the first structure comprises:
forming a first interconnect structure (Fig.5 130; ¶0032) over a first substrate (Fig.5 110; ¶0033), the first interconnect structure (130) comprising a metallization pattern (Fig.5 132; ¶0037);
forming a first through substrate via (TSV) (Fig.5 114; ¶0032) through the first interconnect structure (130) and the first substrate (110); and
forming first bond pads (Fig.5 171; ¶0046) over the first interconnect structure (130) and connected to the first TSV (114) and the metallization pattern (132) of the first interconnect structure (130);
bonding the first structure (100) to a second structure (Fig.5 200; ¶0061);
after bonding, forming a second TSV (Fig.5 181; ¶0098) through the first substrate (110) of the first structure (100) to the first interconnect structure (130), the second TSV (181) having a smaller width (Fig.5 W4; ¶0101) than the first TSV (Fig.5 W2; ¶0101);
thinning the first substrate (114), wherein thinning exposes (114 is exposed from the bottom surface (Fig.5 110b; ¶0033) of the substrate (110)) the first TSV (114); and
forming second bond pads (Fig.5 150; ¶0059) on the first structure (100), the second bond pads (150) being electrically coupled to the first (114) and second (181) TSVs.
Regarding claim 19, Jeon teaches the method of claim 18, further comprising:
bonding the second bond pads (150) of the first structure (100) to a third structure (Fig.1 500; ¶0030), the third structure comprising TSVs (interposers are known to comprise TSVs).
Regarding claim 20, Jeon teaches the method of claim 19, wherein the second structure (200) comprises a semiconductor die (¶0031).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11-17, 21, 23-27 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Shih (US-20210296174-A1).
Regarding claim 11, Jeon teaches a method, comprising:
forming a first structure (Fig.4 100; ¶0031) including a first surface and a second surface opposite the first surface, wherein forming the first structure (100) comprises:
forming a first interconnect structure (Fig.4 130; ¶0032) over a first substrate (Fig.4 110; ¶0033), the first interconnect structure (130) comprising an active metallization pattern (Fig.4 132; ¶0037);
forming a first through substrate via (Fig.4 114; ¶0032) (TSV) through the first interconnect structure (130) and the first substrate (110); and
forming first bond pads (Fig.4 171; ¶0046) over the first interconnect structure (130) and connected to the first TSV (114) and the active metallization pattern (132) of the first interconnect structure (130), the first bond pads (171) being on the first surface of the first structure (100);
forming a second structure (Fig.4 200; ¶0061) including a first surface and a second surface opposite the first surface;
bonding the first surface of the first structure (100) to the first surface of the second structure (200);
after bonding, forming a second TSV (Fig.4 124; ¶0038) from the second surface of the first structure (100) to the first interconnect structure (130), the second TSV (124) having a smaller width (Fig.5 W4; ¶0101) than the first TSV (Fig.5 W2; ¶0101);
exposing the first TSV (114) at the second surface (Fig.4 110b; ¶0033) of the first structure (100); and
forming second bond pads (Fig.4 150; ¶0059) on the second surface of the first structure (100), the second bond pads (150) being electrically coupled to the first (114) and second (124) TSVs.
Jeon does not teach wherein the first structure comprises a guard ring and wherein the guard ring surrounding the first TSV in the first interconnect structure.
Shih teaches a guard ring structure (Fig.1 215; ¶0056 of Shih) that surrounds a conductive line (Fig.1 211 and 207; ¶0056 of Shih).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to surround the TSVs of Jeon (114 and 124 of Jeon) with the guard rings taught by Shih (215 of Shih) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of protecting the TSVs from structural damage and improving mechanical strength (¶0048 of Shih).
Regarding claim 12, the combination of Jeon in view of Shih from claim 11 teaches the method of claim 11, further comprising:
forming a third structure (Fig.4 300; ¶0031 of Jeon) including a first surface and a second surface opposite the first surface; and
bonding the second surface of the first structure (100 of Jeon) to the first surface of the third structure (300 of Jeon) with the second bond pads (150 of Jeon).
Regarding claim 13, the combination of Jeon in view of Shih from claim 11 teaches the method of claim 11, wherein the first (100 of Jeon) and second (200 of Jeon) structures are bonded in a face-to-face configuration (depicted in Fig.4 of Jeon).
Regarding claim 14, the combination of Jeon in view of Shih from claim 13 teaches the method of claim 13, wherein the first (100 of Jeon) and third structures (300 of Jeon) are bonded in a face-to-back configuration (depicted in Fig.4 of Jeon).
Regarding claim 15, the combination of Jeon in view of Shih from claim 12 teaches the method of claim 12, wherein the first (100 of Jeon) and third (300 of Jeon) structures are semiconductor dies, and wherein the second structure (200 of Jeon) is a semiconductor wafer (all three of these components are dies/wafers which are analogous terms).
Regarding claim 16, the combination of Jeon in view of Shih from claim 12 teaches the method of claim 12, further comprising:
bonding the second surface of the third structure (300 of Jeon) to an interposer (Fig.1 500; ¶0030 of Jeon), the third structure (300 of Jeon) being between the first structure (100 of Jeon) and the interposer (500 of Jeon).
Regarding claim 17, the combination of Jeon in view of Shih from claim 16 teaches the method of claim 16, further comprising:
bonding a first die (Fig.1 20; ¶0082 of Jeon) to the interposer (500 of Jeon), the interposer (500 of Jeon) comprising a local interconnect (Fig.1 ML; ¶0090) embedded within the interposer (500 of Jeon), the local interconnect (ML of Jeon) being coupled to the first die (20 of Jeon) and the third structure (300 of Jeon).
Regarding claim 21, Jeon teaches a method, comprising:
forming an interconnect structure (Fig.5 130; ¶0032) over a first side of a first substrate (Fig.5 110; ¶0033), the interconnect structure (130) comprising active metallization patterns (Fig.5 132; ¶0037) electrically coupled to devices (Fig.5 134-136; ¶0044) at the first side of the first substrate (110);
forming a plurality (see Fig.1) of first through substrate vias (TSVs) (Fig.5 114; ¶0032) extending through the interconnect structure (130) and into the first substrate (110), the first TSVs (114) having a first width (Fig.5 W2; ¶0101) and being at a first pitch;
forming first bond pads (Fig.5 171; ¶0046) over the interconnect structure (130), the first bond pads (171) being electrically coupled to the first TSVs (114) and to the active metallization patterns (132);
bonding a second structure (Fig.5 200; ¶0061) to the first bond pads (171);
after the bonding, forming a plurality (see Fig.1) of second TSVs (Fig.5 181; ¶0098) extending from a second side of the first substrate (110) through the first substrate (110) and into the interconnect structure (130), the second TSVs (181) having a second width (Fig.5 W4; ¶0101) smaller than the first width (W2) and being at a second pitch smaller than the first pitch, the second TSVs (181) being laterally between the first TSVs (114);
thinning the first substrate (110) from the second side (Fig.5 110b; ¶0033) to expose the first TSVs (114) and the second TSVs (181); and
forming second bond pads (Fig.5 150; ¶0059) over the second side of the first substrate (110), the second bond pads (150) electrically coupling the first TSVs (114) to a power or ground line and electrically coupling the second TSVs to a signal line.
Jeon does not teach the first interconnect structure comprising guard rings, the guard rings being formed simultaneously with and by same processes as the active metallization patterns;
a first guard ring of the guard rings laterally surrounding a first TSV of the first TSVs; and
a second guard ring of the guard rings laterally surrounding a second TSV of the second TSVs.
Shih teaches a guard ring structure (Fig.1 215; ¶0056 of Shih) that surrounds a conductive line (Fig.1 211 and 207; ¶0056 of Shih).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to surround the TSVs of Jeon (114 and 124 of Jeon) with the guard rings taught by Shih (215 of Shih) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of protecting the TSVs from structural damage and improving mechanical strength (¶0048 of Shih).
Regarding claim 23, the combination of Jeon in view of Shih from claim 21 teaches the method of claim 21, wherein the guard rings (215 of Shih) comprise a shared guard ring (middle instance of 215 of Shih), the shared guard ring being laterally between the first TSV (114 of Jeon) and an adjacent one of the first TSVs (second instance of 114 of Jeon, see Fig.1) and surrounding both the first TSV (114 of Jeon) and the adjacent one of the first TSVs (114 of Jeon).
Regarding claim 24, the combination of Jeon in view of Shih from claim 21 teaches the method of claim 21, wherein the first pitch is in a range from one times the first width to two times the first width (Fig.1 and Fig.5 of Jeon appear to meet this claim).
Regarding claim 25, the combination of Jeon in view of Shih from claim 21 teaches the method of claim 21, wherein a ratio of the first width to the second width is in a range from 1.5 to 70 (Fig.5 of Jeon appears to meet this claim).
Regarding claim 26, the combination of Jeon in view of Shih from claim 21 teaches the method of claim 21, further comprising:
before the bonding, forming a second interconnect structure (Fig.5 140; ¶0047 of Jeon) over the interconnect structure (130 of Jeon) and over the first TSVs (114 of Jeon), the second interconnect structure (140 of Jeon) comprising a top metal (Fig.5 142; ¶0047 of Jeon), wherein the first bond pads (171 of Jeon) are formed over the second interconnect structure (140 of Jeon), and wherein the second TSVs (181 of Jeon) are formed to land on the top metal (142 of Jeon) of the second interconnect structure (140 of Jeon).
Regarding claim 27, the combination of Jeon in view of Shih from claim 21 teaches the method of claim 21, wherein a portion of the first TSV (114 of Jeon) in the interconnect structure (130 of Jeon) has a greater width than a portion of the first TSV (114 of Jeon) in the first substrate (110 of Jeon), and wherein a portion of the second TSV (181 of Jeon) in the first substrate (110 of Jeon) has a greater width than a portion of the second TSV (181 of Jeon) in the interconnect structure (130 of Jeon).
Regarding claim 29, the combination of Jeon in view of Shih from claim 21 teaches the method of claim 21, further comprising:
before the bonding, attaching the first substrate (110 of Jeon) to a carrier (Fig.11A 1000; ¶0120), encapsulating the first substrate (110 of Jeon) with an encapsulant (Fig.1 590; ¶0028 of Jeon); and
planarizing the encapsulant (590 of Jeon) until surfaces of the first bond pads (171 of Jeon), a bonding dielectric layer (Fig.5 170; ¶0045 of Jeon) surrounding the first bond pads (171 of Jeon), and the encapsulant (590 of Jeon) are coplanar.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Shih, and further in view of Kim et al. (US-20250132234-A1).
Regarding claim 22, the combination of Jeon in view of Shih from claim 21 teaches the method of claim 21.
The combination does not teach the method further comprising forming dummy metallization patterns in the interconnect structure simultaneously with the active metallization patterns, the dummy metallization patterns being adjacent the guard rings and electrically isolated from the devices.
Kim teaches a dummy structure (Fig.1 270; ¶0037 of Kim) disposed within a semiconductor device.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include dummy structures within the device taught by Jeon and Shih to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of stress absorption.
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Shih, and further in view of Li et al. (US-20230352406-A1).
Regarding claim 28, the combination of Jeon in view of Shih from claim 21 teaches the method of claim 21.
The combination does not explicitly teach wherein forming the second TSVs comprises filling openings with a conductive material and, after the filling, performing an anneal that reduces extrusion of the conductive material.
Li teaches an annealing process for fabricating TSVs (¶0078 of Li).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, for the anneal process taught by Li to be used because it is a well-known method for fabricating TSVs.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Shih, and further in view of Lee et al. (US-20260248052-A1).
Regarding claim 30, the combination of Jeon in view of Shih from claim 29 teaches the method of claim 29.
The combination does not teach the method further comprising:
before forming the second TSVs, depositing a stop layer over the second side of the first substrate and over the encapsulant;
forming a mask layer over the stop layer; and
patterning openings through the mask layer, the stop layer, the first substrate, and the interconnect structure.
Lee teaches a method of patterning through a mask layer (Claim 13 of Lee).
It would have been obvious for a similar process to be used because patterning through a mask layer is well-known in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US-20240006356-A1 and US-20220084928-A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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