DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species A in the reply filed on July 09, 2026 is acknowledged. In interview with Agent Jay Yin on August 19,2026, incomplete species election was discussed. Applicant chose sub-species i.
Claims 7-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected sub-species, there being no allowable generic or linking claim. Election was made without traverse in the Interview with Agent Jay Yin on August 19, 2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et. al. (US 20190214314 A1), hereinafter Seo, in further view of Kim et. al. (US 20220209013 A1), hereinafter Kim.
Regarding claim 1, Seo teaches a method (Figs 1-19, [0031]), comprising: forming ([0037]) a fin-shaped structure (Fig 3 PFET/NFET stack, [0037]) over a substrate (Fig 3 substrate 102, [0038]), the fin-shaped structure (Fig 3 PFET/NFET stack, [0037]) comprising a plurality of channel layers (Fig 3 unlabeled active channel from Fig 1, [0039]) interleaved by a plurality of sacrificial layers (Fig 3 unlabeled sacrificial material from Fig 1, [0039]); recessing ([0038]) a source/drain region (Fig 4 region containing pocket 304, [0038]) of the fin-shaped structure (Fig 3 PFET/NFET stack, [0037]) to form a source/drain recess (Fig 4 pocket 304, [0038]) that exposes a portion of the substrate (Fig 3 substrate 102, [0038]) and sidewalls of (Fig 4) the plurality of the channel layers (Fig 3 unlabeled active channel from Fig 1, [0039]); selectively and partially recessing ([0039]) sidewalls of the plurality of sacrificial layers (Fig 3 unlabeled sacrificial material from Fig 1, [0039]) to form inner spacer recesses (Fig 4 unlabeled inner spacer recesses, [0039]); forming ([0040]) inner spacers (Fig 5 inner spacers 502, [0040]) in the inner spacer recesses (Fig 4 unlabeled inner spacer recesses, [0039]); forming ([0042]-[0049]) a bottom dielectric layer (Fig 10 oxide protective layer 806, [0043]) to cover the exposed portion of the substrate (Fig 3 substrate 102, [0038])
Seo fails to teach depositing a first epitaxial layer over the inner spacers (Fig 5 inner spacers 502, [0040]) and the exposed sidewalls of the plurality of the channel layers; performing a thermal treatment to reshape the first epitaxial layer; after the performing of the thermal treatment, depositing a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer comprises germanium, wherein the second epitaxial layer is free of germanium.
However, Kim teaches depositing a first epitaxial layer (Fig 11G first epitaxial layer 150L, [0103]) over the inner spacers (Fig 11G internal spacer layer 130, [0101] corresponds to Seo: Fig 5 inner spacers 502, [0040]) and the exposed sidewalls (Fig 11G) of the plurality of the channel layers (Fig 11G channel layers 141, 142, and 143, [0103] corresponds to Seo: Fig 3 unlabeled active channel from Fig 1, [0039]); performing a thermal treatment (high temperature anneal, [0106]) to reshape the first epitaxial layer (Fig 11G first epitaxial layer 150L, [0103]); after the performing of the thermal treatment (high temperature anneal, [0106]), depositing ([0109]) a second epitaxial layer (Fig 11I second epitaxial layer 150B, [0109]) over the first epitaxial layer (Fig 11I first epitaxial layer 150A, [0109]), wherein the first epitaxial layer (Fig 11I first epitaxial layer 150A, [0109]) comprises germanium (SiGe, [0108]), wherein the second epitaxial layer (Fig 11I second epitaxial layer 150B, [0109]) is free of germanium (Si, [0110]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Seo to incorporate the teachings of Kim by forming two epitaxial layers in a source/drain region and performing a thermal treatment on a first epitaxial layer. This would allow for the first epitaxial layer to be formed of materials to restrict short channel effects ([0051]) and the thermal treatment of the first epitaxial layer would be used to reduce structural defects caused by the epitaxial growth ([0056]). This would allow for the second epitaxial layer to have a different impurity and concentration to improve conductivity of the source/drain region ([0053]).
Examiner notes Seo teaches a single epitaxial layer formed of Si ([0051]), SiGe ([0051]), or Si:C ([0053]) among other materials.
Regarding claim 2, Seo as modified in claim 1 teaches the first epitaxial layer (Kim: Fig 11I first epitaxial layer 150A, [0109]) further comprises silicon (Kim: SiGe, [0108]) and at least one n-type dopant (Kim: phosphorous, [0044]).
Regarding claim 3, Seo as modified in claim 1 teaches the thermal treatment (Kim: high temperature anneal, [0106]) comprises a temperature between (Kim: 700°C-750°C, [0108]) about 600°C and about 800°C.
Regarding claim 4, Seo as modified in claim 1 teaches the second epitaxial layer (Kim: Fig 11I second epitaxial layer 150B, [0109]) comprises silicon (Kim: SiC, [0041]), carbon (Kim: SiC, [0041]), and at least one n-type dopant (Kim: phosphorous, [0072]).
Regarding claim 5, Seo as modified in claim 1 teaches before (Fig 11G) the performing of the thermal treatment (Kim: high temperature anneal, [0106]), the first epitaxial layer (Kim: Fig 11G first epitaxial layer 150A, [0109]) comprises a wavy sidewall (Fig 11G), wherein, after the performing of the thermal treatment (Kim: high temperature anneal, [0106]) , the wavy sidewall becomes a flat sidewall (Fig 11H).
Regarding claim 6, Seo as modified in claim 1 teaches after the depositing ([0109]) of the second epitaxial layer (Kim: Fig 11I second epitaxial layer 150B, [0109]), a bottom surface (Seo: Fig 15 source and drains 1502, [0053]) of the second epitaxial layer (Seo: Fig 15 inner portion of source and drains 1502, [0053] corresponds to Kim: Fig 11I second epitaxial layer 150B, [0109]; See note below) is spaced apart from the bottom dielectric layer (Fig 10 oxide protective layer 806, [0043]) by a gap (Fig 15 unlabeled gap between the bottom of source and drains 1502 and protective layer 806).
Examiner notes one having ordinary skill in the art before the effective filing date of the claimed invention would recognize the inner portion of 1502 from Kim would correspond to the second epitaxial layer of Kim. This is because the layers are formed epitaxially and the bottom dielectric layer of Seo prevent epitaxial growth from occurring. Thus, the only place for growth would be on the surface of the first epitaxial layer. This would form a structure similar to 1502.
Claims 21-31 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et. al. (US 20190214314 A1), hereinafter Seo, in further view of Kim et. al. (US 20220209013 A1), hereinafter Kim, in view of Lee et.al. (US 20210126135 A1), hereinafter Lee.
Regarding claim 21, Seo teaches a method (Figs 1-19, [0031]), comprising: depositing ([0032]), over a substrate (Fig 3 substrate 102, [0038]), a stack (Fig 1, [0032]) comprising a plurality of channel layers (Fig 1 active channel, [0039]) interleaved by a plurality of sacrificial layers (Fig 1 sacrificial material, [0039]); patterning ([0037]) the stack and a portion of the substrate (Fig 3 substrate 102, [0038]) to form a fin-shaped structure (Fig 3 PFET/NFET stack, [0037]), the fin-shaped structure (Fig 3 PFET/NFET stack, [0037]) comprising a base portion (Fig 3 portion of substrate under the PFET/NFET stack) formed from the substrate (Fig 3 substrate 102, [0038]) and a stack portion (Fig 3 PFET/NFET stack, [0037]) formed from the stack (Fig 1, [0032]); recessing ([0038]) a source/drain region (Fig 4 region containing pocket 304, [0038]) of the fin-shaped structure (Fig 3 PFET/NFET stack, [0037]) to form a source/drain recess (Fig 4 pocket 304, [0038]) that exposes a portion (Fig 4 pocket 304, [0038]) of the base portion (Fig 3 portion of substrate under the PFET/NFET stack), sidewalls of the plurality of channel layers (Fig 3 unlabeled active channel from Fig 1, [0039]) and sidewalls of the plurality of sacrificial layers (Fig 3 unlabeled sacrificial material from Fig 1, [0039]); recessing ([0039]) the exposed sidewalls of the plurality of sacrificial layers (Fig 3 unlabeled sacrificial material from Fig 1, [0039]) to form inner spacer recesses (Fig 4 unlabeled inner spacer recesses, [0039]); forming ([0040]) inner spacers (Fig 5 inner spacers 502, [0040]) in the inner spacer recesses (Fig 4 unlabeled inner spacer recesses, [0039]); forming ([0042]-[0049]) a bottom dielectric layer (Fig 10 oxide protective layer 806, [0043]) to cover the exposed portion (Fig 4 pocket 304, [0038]) of the base portion (Fig 3 portion of substrate under the PFET/NFET stack) wherein the bottom dielectric layer (Fig 10 oxide protective layer 806, [0043]) interfaces at least a portion of a bottommost one (Examiner notes that Seo suggests that the bottom dielectric layer interfaces at least a portion of a bottommost one of the inner spacers; Fig 6 and [0042] teaches a SiGe layer is grown in the pocket; Figs 6-9 show the protective layer 806 extending past the top of the pocket and interfacing with a portion of the bottommost inner spacer 502) of the inner spacers (Fig 5 inner spacers 502, [0040]).
Seo fails to teach forming an isolation feature to interface sidewalls of the base portion; depositing a first epitaxial layer over the inner spacers (Fig 5 inner spacers 502, [0040]) and the exposed sidewalls of the plurality of the channel layers; performing a thermal treatment to reshape the first epitaxial layer; and after the performing of the thermal treatment, depositing a second epitaxial layer over the first epitaxial layer, wherein the bottom dielectric layer (Fig 10 oxide protective layer 806, [0043]) interfaces at least a portion of a bottommost one of the inner spacers (Fig 5 inner spacers 502, [0040]), wherein a profile of the first epitaxial layer after the thermal treatment is different from a profile of the first epitaxial layer before the thermal treatment.
However, Lee teaches forming an isolation feature (Fig 3 isolation layer 115, [0018]) to interface sidewalls of the base portion (Fig 3 sidewalls of base portion 102 corresponds to Seo: Fig 3 portion of substrate under the PFET/NFET stack).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Seo to incorporate the teachings of Lee by having isolation features. This would separate the fin structures ([0018]). Examiner notes that while Seo fails to teach isolation features, one having ordinary skill in the art before the effective filing date of the claimed invention would recognize that some isolation feature would need to be used to separate the different transistors in a device (NFET and PFET are formed side-by-side on a wafer, [0031]).
Seo and Lee fail to teach depositing a first epitaxial layer over the inner spacers (Fig 5 inner spacers 502, [0040]) and the exposed sidewalls of the plurality of the channel layers; performing a thermal treatment to reshape the first epitaxial layer; and after the performing of the thermal treatment, depositing a second epitaxial layer over the first epitaxial layer, wherein the bottom dielectric layer (Fig 10 oxide protective layer 806, [0043]) interfaces at least a portion of a bottommost one of the inner spacers (Fig 5 inner spacers 502, [0040]), wherein a profile of the first epitaxial layer after the thermal treatment is different from a profile of the first epitaxial layer before the thermal treatment.
However, Kim teaches depositing a first epitaxial layer (Fig 11G first epitaxial layer 150L, [0103]) over the inner spacers (Fig 11G internal spacer layer 130, [0101] corresponds to Seo: Fig 5 inner spacers 502, [0040]) and the exposed sidewalls (Fig 11G) of the plurality of the channel layers (Fig 11G channel layers 141, 142, and 143, [0103] corresponds to Seo: Fig 3 unlabeled active channel from Fig 1, [0039]); performing a thermal treatment (high temperature anneal, [0106]) to reshape the first epitaxial layer (Fig 11G first epitaxial layer 150L, [0103]); after the performing of the thermal treatment (high temperature anneal, [0106]), depositing ([0109]) a second epitaxial layer (Fig 11I second epitaxial layer 150B, [0109]) over the first epitaxial layer (Fig 11I first epitaxial layer 150A, [0109]), wherein a profile (Fig 11G inner sidewall of first epitaxial layer 150A) of the first epitaxial layer (Fig 11H first epitaxial layer 150A, [0109]) after the thermal treatment (high temperature anneal, [0106]) is different (wavy to straight) from a profile (Fig 11G inner sidewall of first epitaxial layer 150A) of the first epitaxial layer (Fig 11G first epitaxial layer 150A, [0109]) before the thermal treatment (high temperature anneal, [0106]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Seo to incorporate the teachings of Kim by forming two epitaxial layers in a source/drain region and performing a thermal treatment on a first epitaxial layer. This would allow for the first epitaxial layer to be formed of materials to restrict short channel effects ([0051]) and the thermal treatment of the first epitaxial layer would be used to reduce structural defects caused by the epitaxial growth ([0056]). This would allow for the second epitaxial layer to have a different impurity and concentration to improve conductivity of the source/drain region ([0053])
Examiner notes Seo teaches a single epitaxial layer formed of Si ([0051]), SiGe ([0051]), or Si:C ([0053]) among other materials.
Regarding claim 22, Seo as modified in claim 21 teaches the first epitaxial layer (Fig 11I first epitaxial layer 150A, [0109]) comprises germanium (SiGe, [0108]), wherein the second epitaxial layer (Fig 11I second epitaxial layer 150B, [0109]) is free of germanium (Si, [0110]).
Regarding claim 23, Seo as modified in claim 21 teaches the first epitaxial layer (Kim: Fig 11I first epitaxial layer 150A, [0109]) further comprises silicon (Kim: SiGe, [0108]) and at least one n-type dopant (Kim: phosphorous, [0044]).
Regarding claim 24, Seo as modified in claim 21 teaches the thermal treatment (Kim: high temperature anneal, [0106]) comprises a temperature between (Kim: 700°C-750°C, [0108]) about 600°C and about 800°C.
Regarding claim 25, Seo as modified in claim 21 teaches the second epitaxial layer (Kim: Fig 11I second epitaxial layer 150B, [0109]) comprises silicon (Kim: SiC, [0041]), carbon (Kim: SiC, [0041]), and at least one n-type dopant (Kim: phosphorous, [0072]).
Regarding claim 26, Seo as modified in claim 25 fails to teach a carbon content in the second epitaxial layer is smaller than 2%.
However, Seo teaches forming an epitaxially grown Si:C source and drain that can then be doped with an n-type dopant ([0052]). Kim teaches the second epitaxial layer may be formed of silicon and/or silicon carbide as a base material prior to dopants ([0041] and [0070]). Further, Kim teaches the second epitaxial layer has a higher dopant concentration ([0053]) and some of the dopants from the second epitaxial layer may diffuse into the first epitaxial layer ([0054]). Lee teaches carbon is used in silicon epitaxial layers to impede the out-diffusion of the other n-type dopants ([0044]). Further, Lee teaches the carbon concentration has a range of 0.1 at% - 5 at% ([0044]). Examiner is interpreting the percent limitation to mean atomic percent since the disclosure does not provide any further information as to the specific kind of percent (i.e. the kind of percent, could be but not limited to at%, wt%, vol%).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Seo to incorporate the teachings of Kim and Lee by having a carbon content of the second epitaxial layer being smaller than 2%. One having ordinary skill in the art would have modified the materials used in the epitaxial growth of the second epitaxial layer to have the carbon content to be within a certain range, in order to impede out-diffusion of other n-type dopants from higher concentration layers to lower concentration areas, as taught by Lee, with a reasonable expectation of success. MPEP 2143(I)(G)
Regarding the range taught by Lee, the entire range of 0.1 at% - 5 at% would perform the same function of impeding the out-diffusion of the other n-type dopants. Because there is no allegation of criticality and no evidence demonstrating a difference across the range, Lee discloses the claimed range with sufficient specificity. MPEP 2131.03 (II)
Regarding claim 27, Seo as modified in claim 21 teaches after the depositing ([0109]) of the second epitaxial layer (Kim: Fig 11I second epitaxial layer 150B, [0109]), a bottom surface (Seo: Fig 15 source and drains 1502, [0053]) of the second epitaxial layer (Seo: Fig 15 inner portion of source and drains 1502, [0053] corresponds to Kim: Fig 11I second epitaxial layer 150B, [0109]; See note below) is spaced apart from the bottom dielectric layer (Fig 10 oxide protective layer 806, [0043]) by a gap (Fig 15 unlabeled gap between the bottom of source and drains 1502 and protective layer 806).
Examiner notes one having ordinary skill in the art before the effective filing date of the claimed invention would recognize the inner portion of 1502 from Kim would correspond to the second epitaxial layer of Kim. This is because the layers are formed epitaxially and the bottom dielectric layer of Seo prevent epitaxial growth from occurring. Thus, the only place for growth would be on the surface of the first epitaxial layer. This would form a structure similar to 1502.
Regarding claim 28, Seo teaches a method (Figs 1-19, [0031]), comprising: depositing ([0032]), over a substrate (Fig 3 substrate 102, [0038]), a stack (Fig 1, [0032]) comprising a plurality of channel layers (Fig 3 unlabeled active channel from Fig 1, [0039]) interleaved by a plurality of sacrificial layers (Fig 3 unlabeled sacrificial material from Fig 1, [0039]); patterning ([0037]) the stack and a portion of the substrate (Fig 3 substrate 102, [0038]) to form a fin-shaped structure (Fig 3 PFET/NFET stack, [0037]), the fin-shaped structure (Fig 3 PFET/NFET stack, [0037]) comprising a base portion (Fig 3 portion of substrate under the PFET/NFET stack) formed from the substrate (Fig 3 substrate 102, [0038]) and a stack portion (Fig 3 PFET/NFET stack, [0037]) formed from the stack (Fig 1, [0032]); recessing ([0038]) a source/drain region (Fig 4 region containing pocket 304, [0038]) of the fin-shaped structure (Fig 3 PFET/NFET stack, [0037]) to form a source/drain recess (Fig 4 pocket 304, [0038]) that exposes a portion (Fig 4 pocket 304, [0038]) of the base portion (Fig 3 portion of substrate under the PFET/NFET stack), sidewalls of the plurality of channel layers (Fig 3 unlabeled active channel from Fig 1, [0039]) and sidewalls of the plurality of sacrificial layers (Fig 3 unlabeled sacrificial material from Fig 1, [0039]); recessing ()[0039] the exposed sidewalls of the plurality of sacrificial layers (Fig 3 unlabeled sacrificial material from Fig 1, [0039]) to form inner spacer recesses (Fig 4 unlabeled inner spacer recesses, [0039]); forming ([0040]) inner spacers (Fig 5 inner spacers 502, [0040]) in the inner spacer recesses (Fig 4 unlabeled inner spacer recesses, [0039]); forming ([0042]-[0049]) a bottom dielectric layer (Fig 10 oxide protective layer 806, [0043]) to cover the exposed portion (Fig 4 pocket 304, [0038]) of the base portion (Fig 3 portion of substrate under the PFET/NFET stack).
Seo fails to teach forming an isolation feature to interface sidewalls of the base portion; depositing a first epitaxial layer over the inner spacers (Fig 5 inner spacers 502, [0040]) and the exposed sidewalls of the plurality of the channel layers; performing a thermal treatment to reshape the first epitaxial layer; and after the performing of the thermal treatment, depositing a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer comprises germanium, wherein the second epitaxial layer is free of germanium, wherein the first epitaxial layer and the second epitaxial layer comprise an n- type dopant, wherein a concentration of the n-type dopant in the second epitaxial layer is greater than a concentration of the n-type dopant in the first epitaxial layer.
However, Lee teaches forming an isolation feature (Fig 3 isolation layer 115, [0018]) to interface sidewalls of the base portion (Fig 3 sidewalls of base portion 102 corresponds to Seo: Fig 3 portion of substrate under the PFET/NFET stack).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Seo to incorporate the teachings of Lee by having isolation features. This would separate the fin structures ([0018]). Examiner notes that while Seo fails to teach isolation features, one having ordinary skill in the art before the effective filing date of the claimed invention would recognize that some isolation feature would need to be used to separate the different transistors in a device (NFET and PFET are formed side-by-side on a wafer, [0031]).
Seo and Lee fail depositing a first epitaxial layer over the inner spacers and the exposed sidewalls of the plurality of the channel layers; performing a thermal treatment to reshape the first epitaxial layer; and after the performing of the thermal treatment, depositing a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer comprises germanium, wherein the second epitaxial layer is free of germanium, wherein the first epitaxial layer and the second epitaxial layer comprise an n- type dopant, wherein a concentration of the n-type dopant in the second epitaxial layer is greater than a concentration of the n-type dopant in the first epitaxial layer.
However, Kim teaches depositing a first epitaxial layer (Fig 11G first epitaxial layer 150L, [0103]) over the inner spacers (Fig 11G internal spacer layer 130, [0101] corresponds to Seo: Fig 5 inner spacers 502, [0040]) and the exposed sidewalls (Fig 11G) of the plurality of the channel layers (Fig 11G channel layers 141, 142, and 143, [0103] corresponds to Seo: Fig 3 unlabeled active channel from Fig 1, [0039]); performing a thermal treatment (high temperature anneal, [0106]) to reshape the first epitaxial layer (Fig 11G first epitaxial layer 150L, [0103]); after the performing of the thermal treatment (high temperature anneal, [0106]), depositing ([0109]) a second epitaxial layer (Fig 11I second epitaxial layer 150B, [0109]) over the first epitaxial layer (Fig 11I first epitaxial layer 150A, [0109]), wherein the first epitaxial layer (Fig 11I first epitaxial layer 150A, [0109]) comprises germanium (SiGe, [0108]), wherein the second epitaxial layer (Fig 11I second epitaxial layer 150B, [0109]) is free of germanium (Si, [0110]), wherein the first epitaxial layer (Fig 11I first epitaxial layer 150A, [0109]) and the second epitaxial layer (Fig 11I second epitaxial layer 150B, [0109]) comprise an n- type dopant (phosphorous; first epitaxial layer, [0044] and second epitaxial layer, [0072]), wherein a concentration of the n-type dopant (phosphorous; first epitaxial layer, [0044] and second epitaxial layer, [0072]) in the second epitaxial layer (Fig 11I second epitaxial layer 150B, [0109]) is greater ([0053]) than a concentration of the n-type dopant (phosphorous; first epitaxial layer, [0044] and second epitaxial layer, [0072]) in the first epitaxial layer (Fig 11I first epitaxial layer 150A, [0109]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Seo to incorporate the teachings of Kim by forming two epitaxial layers in a source/drain region and performing a thermal treatment on a first epitaxial layer. This would allow for the first epitaxial layer to be formed of materials to restrict short channel effects ([0051]) and the thermal treatment of the first epitaxial layer would be used to reduce structural defects caused by the epitaxial growth ([0056]). This would allow for the second epitaxial layer to have a different impurity and concentration to improve conductivity of the source/drain region ([0053])
Examiner notes Seo teaches a single epitaxial layer formed of Si ([0051]), SiGe ([0051]), or Si:C ([0053]) among other materials.
Regarding claim 29, Seo as modified in claim 28 teaches the bottom dielectric layer (Seo: Fig 10 oxide protective layer 806, [0043]) interfaces at least a portion of a bottommost one (Examiner notes that Seo suggests that the bottom dielectric layer interfaces at least a portion of a bottommost one of the inner spacers; Fig 6 and [0042] teaches a SiGe layer is grown in the pocket; Figs 6-9 show the protective layer 806 extending past the top of the pocket and interfacing with a portion of the bottommost inner spacer 502) of the inner spacers (Seo: Fig 5 inner spacers 502, [0040])
Regarding claim 30, Seo as modified in claim 28 teaches before (Fig 11G) the performing of the thermal treatment (Kim: high temperature anneal, [0106]), the first epitaxial layer (Kim: Fig 11G first epitaxial layer 150A, [0109]) comprises a wavy sidewall (Fig 11G), wherein, after the performing of the thermal treatment (Kim: high temperature anneal, [0106]) , the wavy sidewall becomes a flat sidewall (Fig 11H).
Regarding claim 31, Seo as modified in claim 28 teaches after the depositing ([0109]) of the second epitaxial layer (Kim: Fig 11I second epitaxial layer 150B, [0109]), a bottom surface (Seo: Fig 15 source and drains 1502, [0053]) of the second epitaxial layer (Seo: Fig 15 inner portion of source and drains 1502, [0053] corresponds to Kim: Fig 11I second epitaxial layer 150B, [0109]; See note below) is spaced apart from the bottom dielectric layer (Fig 10 oxide protective layer 806, [0043]) by a gap (Fig 15 unlabeled gap between the bottom of source and drains 1502 and protective layer 806).
Examiner notes one having ordinary skill in the art before the effective filing date of the claimed invention would recognize the inner portion of 1502 from Kim would correspond to the second epitaxial layer of Kim. This is because the layers are formed epitaxially and the bottom dielectric layer of Seo prevent epitaxial growth from occurring. Thus, the only place for growth would be on the surface of the first epitaxial layer. This would form a structure similar to 1502.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Song et. al. (US 20180190829 A1) teaches a method to form a structure similar to Seo, wherein the source/drain region is a single layer.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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