DETAILED ACTION
Response to Arguments
Applicant's arguments filed 09/19/2025 have been fully considered but they are not persuasive.
Applicant argues:
[Pages 8-9] of REMARKS,
These amendments and remarks are filed in response to the Office Action dated December 2, 2025. For the following reasons, this application should be allowed and the case passed to issue. No new matter is introduced by this response. See e.g., FIGS. 19A-19B, 20A-20C, FIG. 21, and FIG. 23.
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Amended independent claim 1 recites, in pertinent part, a first width W1 at a first level H1 from an upper surface of the isolation insulating layer, as viewed in cross-section along the first direction, a second width W2 at a second level H2 from the upper surface of the isolation insulating layer, as viewed in cross-section along the first direction, and a third width W3 at the upper surface of the isolation insulating layer, as viewed in cross-section along the first direction, wherein the first level H1 corresponds to a level of the top of the fin structure, H2 equal to 0.45H1, the first width W1, the second width W2 and the third width W3 are different from each other, a ratio of W1 : W2 : W3 is 1 : 0.73 to 0.81 : 0.82 to 0.88, and the first width W1 is a maximum width of the lower portion, the second width W2 is a minimum width of the lower portion, and wherein a side surface of the lower portion continuously reduces in width from the first level H1 to the second level H2, and continuously increases in width from the second level H2 to the upper surface of the isolation insulating layer. Applicant amends independent claims 9 and 16 in a substantially similar manner as independent claim 1. As such, amended independent claims 1, 9, and 16 and all claims dependent thereon are patentable over the cited references.
Examiner’s reply:
Referring to the fig. 6A, the lower portion of the gate electrode (160) shrinks continuously from an upper surface of the fin structure (122) down to the approximate middle point of the lower portion and then expands down to the level of the isolation structure (140) as newly included limitations in the independent claims 1, 9 and 16.
Referring to the applicant’s fig. 20A, the width of the lower portion gate electrode changes (decreases and increases) continuously and linearly (linear slope).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6-7, 9, 14-16, 21, 23-26, 28 and 30 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Chen et al. (US 20160093537 A1, hereinafter Chen537) of record.
Regarding independent claim 1, Chen537 teaches, “A semiconductor device (100, fig. 1-9; ¶¶ 0015-0051), comprising:
a fin structure (122, fig. 1) protruding from an isolation insulating layer (140) disposed over a substrate (110) and extending in a first direction,
wherein the fin structure (122) has a channel region (¶ 0022);
a source/drain region (¶ 0022) disposed over the substrate (110);
a gate structure including a gate dielectric layer (150/312) disposed over the channel region and a gate electrode layer (160/170) disposed over the gate dielectric layer (150),
wherein the gate structure extends in a second direction crossing the first direction,
wherein the gate structure includes a lower portion (162, fig. 6A-C) below a level of a top of the channel region (upper level of 122, fig. 1) and above an upper surface of the isolation insulating layer (140), and
the lower portion of the gate structure has:
a first width W1 (164, fig. 6A) at a first level H1 (the level of the top of the fin structure 122) from an upper surface of the isolation insulating layer (144), as viewed in cross-section along the first direction (Z),
a second width W2 at a second level H2 from the upper surface of the isolation insulating layer (referring to fig. 1 and 6A, 6C, H2 can be selected as a height from the upper surface of 140 as 0.45 H1, approximately it will be around 163 and width will be approximately 166 which is subjected to optimization) as viewed in cross-section along the first direction (Z), and
a third width W3 (165, fig. 6A) at the upper surface of the isolation insulating layer (140) as viewed in cross-section along the first direction (Z),
wherein the first level H1 corresponds to a level of the top of the fin structure (122),
H2 equal to 0.45 H1,
the first width W1 (164), the second width W2 (approximately 166) and the third width W3 (165) are different from each other, and
(a ratio of W1:W2:W3 is 1:0.73 to 0.81:0.82 to 0.88), and
wherein the first width W1 is a maximum width of the lower portion, the second width W2 is a minimum width of the lower portion, and wherein a side surface of the lower portion continuously reduces in width from the first level H1 to the second level H2, and continuously increases in width from the second level H2 to the upper surface of the isolation insulating layer (fig. 6A)”.
Regarding the limitataion, “a ratio of W1:W2:W3 is 1:0.73 to 0.81:0.82 to 0.88”, Chen537 does not explicitly disclose the particular claimed value. However, Chen537 teaches in reference to the fig. 6A, W1>W3 (‘The second width 165 is smaller than the first width 164’, ¶ 0031), W2<W1 and W2<W3 (‘the third width 166 is smaller than the first width 164 and the second width 165’, ¶ 0032). These teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization.
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The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding independent claim 9, Chen537 teaches, “A semiconductor device (100, fig. 1-9; ¶¶ 0015-0051), comprising:
a fin structure (122, fig. 1) protruding from an isolation insulating layer (140) disposed over a substrate (110) and extending in a first direction (vertical),
wherein the fin structure (122) has a channel region (¶ 0022);
a source/drain region (¶ 0022) disposed over the substrate (110),
wherein the source/drain region includes at least one layer of Si, SiP, SiC, SiCP, Ge, SiGe, GeSn, or SiGeSn (¶ 0041); and
a gate structure including a gate dielectric layer (150/312) disposed over the channel region and a gate electrode layer (160/170) disposed over the gate dielectric layer (150),
wherein the gate structure extends in a second direction (horizontal) crossing the first direction (vertical),
the gate structure includes a lower portion (162, fig. 6A-C) below a level of a top of the channel region (upper level of 122, fig. 1) and above an upper surface of the isolation insulating layer (140), and
the lower portion of the gate structure has:
a first width W1 (164, fig. 6A) at a first level H1 (the level of the top of the fin structure 122) from an upper surface of the isolation insulating layer (144), as viewed in cross-section along the first direction,
a second width W2 at a second level H2 from the upper surface of the isolation insulating layer (referring to fig. 1 and 6A, 6C, H2 can be selected as a height from the upper surface of 140 as 0.45 H1, approximately it will be around 163 and width will be approximately 166), as viewed in cross-section along the first direction, and
a third width W3 (165, fig. 6A) at the upper surface of the isolation insulating layer (140), as viewed in cross-section along the first direction,
wherein the first level H1 corresponds to a level of the top of the fin structure (122),
H2 is equal to 0.45 H1,
the first width W1 (164), the second width W2 (approximately 166) and the third width W3 (165) are different from each other, and
(a ratio of W1:W2:W3 is 1:0.73 to 0.81:0.82 to 0.88), and
wherein the first width W1 is a maximum width of the lower portion, the second width W2 is a minimum width of the lower portion, and wherein a side surface of the lower portion continuously reduces in width from the first level H1 to the second level H2, and continuously increases in width from the second level H2 to the upper surface of the isolation insulating layer (fig. 6A)”.
Regarding the limitataion, “a ratio of W1:W2:W3 is 1:0.73 to 0.81:0.82 to 0.88”, Chen537 does not explicitly disclose the particular claimed value. However, Chen537 teaches in reference to the fig. 6A, W1>W3 (‘The second width 165 is smaller than the first width 164’, ¶ 0031), W2<W1 and W2<W3 (‘the third width 166 is smaller than the first width 164 and the second width 165’, ¶ 0032). These teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization.
The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding independent claim 16, Chen537 teaches, “A semiconductor device (100, fig. 1-9; ¶¶ 0015-0051), comprising:
a fin (122, fig. 1) protruding from an insulating layer (140) disposed over a substrate (110) and extending in a first direction,
a high-k gate dielectric layer (150/312, ¶ 0025) disposed over the fin; and
a metal gate electrode layer (160/170, ¶ 0039) disposed over the high-k dielectric layer (150/312),
wherein the metal gate electrode extends in a second direction (horizontal) crossing the first direction (vertical),
the metal gate electrode layer (160/170) includes an upper portion (161) extending above a top of the fin (122) and a lower portion (162) between the top of the fin (122) and an upper surface of the insulating layer (140), and
the lower portion of the metal gate electrode layer (162) has:
a first width W1 (164, fig. 6A) at a first level H1 (the level of the top of the fin structure 122) from an upper surface of the insulating layer (140), as viewed in cross-section along the first direction,
a second width W2 at a second level H2 from the upper surface of the insulating layer (referring to fig. 1 and 6A, 6C, H2 can be selected as a height from the upper surface of 140 as 0.45 H1, approximately it will be around 163 and width will be approximately 166), as viewed in cross-section along the first direction, and
a third width W3 at the upper surface of the insulating layer, as viewed in cross-section along the first direction
wherein the first level H1 corresponds to the level of the top of the fin (122),
H2 equal to 0.45 H1,
the first width W1 (164), the second width W2 (approximately 166) and the third width W3 (165) are different from each other, and
(a ratio of W1:W2:W3 is 1:0.73 to 0.81:0.82 to 0.88) , and
wherein the first width W1 is a maximum width of the lower portion, the second width W2 is a minimum width of the lower portion, and wherein a side surface of the lower portion continuously reduces in width from the first level H1 to the second level H2, and continuously increases in width from the second level H2 to the upper surface of the isolation insulating layer (fig. 6A)”.
Regarding the limitataion, “a ratio of W1:W2:W3 is 1:0.73 to 0.81:0.82 to 0.88”, Chen537 does not explicitly disclose the particular claimed value. However, Chen537 teaches in reference to the fig. 6A, W1>W3 (‘The second width 165 is smaller than the first width 164’, ¶ 0031), W2<W1 and W2<W3 (‘the third width 166 is smaller than the first width 164 and the second width 165’, ¶ 0032). These teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization.
The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 6 and 14 and 21, Chen537 further teaches, wherein the gate electrode layer (160/170, ¶ 0039) is a metal layer.
Regarding claim 7 and 15, Chen537 further teaches, wherein the gate dielectric layer (150/312, ¶ 0025) is a high-k dielectric layer.
Regarding claim 23, Chen537 further teaches, wherein the high-k dielectric layer (150/312, ¶ 0025) is made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-A1203) alloy, or combinations thereof”.
Regarding claim 24, 25 and 26, “The semiconductor device of claim 1, wherein the ratio of W1: W2: W3 is 1: 0.77: 0.85”, Chen537 does not explicitly disclose the particular claimed value. However, Chen537 teaches in reference to the fig. 6A, W1>W3 (‘The second width 165 is smaller than the first width 164’, ¶ 0031), W2<W1 and W2<W3 (‘the third width 166 is smaller than the first width 164 and the second width 165’, ¶ 0032). These teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization.
The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 28 and 30, Chen537 further teaches, “wherein the high-k dielectric layer (312, ¶ 0025) is made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, or combinations thereof”.
Claims 22, 27, 29, 31 and 32 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Chen537 of record as applied to claim 6, 14 and 21 as above, and further in view of Hsiao et al. (US 20170098711 A1, hereinafter Hsiao711) of record.
Regarding claim 22, 27 and 29, Chen537 teaches all the limitations of claim 6, 14 and 21.
But Chen537 is silent upon the provision of wherein the gate electrode is made of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TIN, WN, TiAl, TiAIN, TaCN, TaC, TaSiN, or combinations thereof.
However, Hsiao711 teaches a similar FinFET device (fig. 1H-1) comprising a a gate electrode (118, ¶ 0046) made of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TIN, WN, TiAl, TiAIN, TaCN, TaC, TaSiN, or combinations thereof.
It would have been obvious to one having ordinary skill in the art before the effective filling date of the invention was made to form the gate electrode with metal, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (See MPEP2144.07).
Regarding claim 31, Chen537 and Hsiao711 further teach, “The semiconductor device of claim 9, further comprising a silicide layer (¶ 0051, Hsiao711) selected from the group consisting of WSi, CoSi, NiSi, MoSi, and TaSi disposed over the source/drain region (112)”.
Regarding claim 32, Chen537 and Hsiao711 further teach, “The semiconductor device of claim 31, further comprising a conductive layer (122, ¶ 0051) made of at least one of W, Co, Ni, Mo, and Ta disposed over the silicide layer”.
Claim 33 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Chen537 and Hsiao711 of record as applied to claim 32 as above, and further in view of Wang et al. (US 20190288084 A1, hereinafter Wang‘084).
Regarding claim 33, Chen537 and Hsiao711 teach all the limitations of claim 32.
But Chen537 and Hsiao711 are silent upon the provision of wherein the semiconductor device of claim 32, further comprising at least one work function adjustment layer disposed between the gate dielectric layer and the gate electrode, wherein the work function adjustment layer is selected from the group consisting of TiN, TaN, TaAlIC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TiAlC, and combinations thereof, wherein the work function adjustment layer and the gate electrode are made of different materials.
However, Wang‘084 teach a similar device comprising at least one work function adjustment layer (54, fig. 14A-14C) disposed between the gate dielectric layer (53) and the gate electrode (55), wherein the work function adjustment layer (54, ¶ 0044) is selected from the group consisting of TiN, TaN, TaAlIC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TiAlC, and combinations thereof, wherein the work function adjustment layer and the gate electrode (55, ¶ 0045) are made of different materials.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Chen537, Hsiao711 and Wang‘084 et al. to a work function layer with the gate electrode according to the teachings of Wang‘084 as the work function adjustment layer tunes the work function of the device. See Wang‘084, ¶ 0044.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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