DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims 1-3 & 5-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8, 9, 10, & 12-14 of U.S. Patent No. 12,009,427 in view of Ching (US Pub no. 2016/0308048 A1)
Regarding clam 1, A semiconductor device, comprising: a fin structure extending in a first direction disposed over a substrate(10)[0020], the fin structure(40) including a channel layer disposed over an oxide layer; a gate electrode layer (60)extending in a second direction over the channel layer, source/drain regions disposed in the fin structure on opposing sides of the gate electrode layer, wherein the source/drain regions include a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, and a fourth epitaxial layer arranged in order in a third direction perpendicular to the first and second directions, wherein the first, second, third, and fourth epitaxial layers have different compositions; and a dielectric layer comprising a first portion and a second portion, wherein the first portion is disposed between the oxide layer and the first epitaxial layer along the first direction , and the second portion is disposed over the fourth epitaxial layer. (claim 8 of 12,009,427)
Claim 8 of 12,009,427 fails to teach wherein the second direction crosses the first direction.
However, Ching et al discloses wherein the second direction crosses the first direction (fig. 8). It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify Claim 8 of 12,009,427 of Ching et al since it is a structural relationship of the features of a Fin FET device .
Regarding claim 2, wherein the oxide layer includes SiGe oxide or Ge oxide. (claim 9 of 12,009,427)
Regarding claim 3, wherein the dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. (Claim 10 of 12,009,427)
Regarding claim 5, wherein the epitaxial layers include at least one of SiC, SiP, SiGe, and Ge (claim 12 of 12,009,427)
Regarding claim 6, further comprising side wall insulating layers
disposed over side walls of the gate electrode layer. (claim 13 of 12,009,427)
Regarding claim 7, wherein the second portion of the dielectric layer is in contact with the side wall insulating layers. (claim 14 of 12,009,427)
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8-13is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ching (US Pub no. 2016/0308048 A1)
Regarding claim 8, Ching et al discloses A semiconductor device, comprising:
a fin (40) extending in a first direction disposed over a substrate(10)[0020], the fin (40)including a channel layer (42)disposed over an oxide layer(25 or 50) [0023][0028];
a gate electrode(60) extending in a second direction over the channel layer(42) [0029] fig. 8, wherein the second direction crosses the first direction fig 8; source/drain regions(80) disposed in the fin structure (40)on opposing sides of the gate electrode layer(60),wherein the source/drain regions(80) include a first layer(81), a second layer(82), a third layer(83), and a fourth layer(84) arranged in order in a third direction perpendicular to the first and second directions[0048-0052] fig. 19a, wherein the first and second layers(81 & 82) have different compositions[0048-0049], the second and third layers (82-83)have different compositions[0049] & 0051], and the third and fourth layers(83 and 84) have different compositions[0051-0052]; and a first dielectric layer (25 or 71 a-Si)disposed between the oxide layer(25 or 50) and the first layer(81) fig. 19a, wherein the second layer (82)contacts the first dielectric layer(71), the first layer(81), the channel layer(42), and the third layer(83) fig. 19a.
Regarding claim 9,Ching et al discloses wherein the oxide layer (25) includes SiGe oxide or Ge oxide[0023].
Regarding claim 10, Ching et al discloses wherein the first dielectric layer (25) includes silicon oxide[0023].
Regarding claim 11, Ching et al discloses wherein the first layer(81), second layer(82), third layer(83), and fourth layer(84) include at least one of SiC, SiP, SiGe, and Ge[0049-0052].
Regarding claim 12, further comprising side wall insulating layers(120a,b)
disposed over the gate electrode(60)[0046].
Regarding claim 13, Ching et al discloses wherein a second dielectric layer(90) is
disposed over the side wall insulating layers(120ab) and the fourth layer(84 or 80) fig 27.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, 6, 7, 8, 10-17, 19, & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2016/0027918 A1-cited in IDS) in view of Tsai (US Pub no. 2016/0254351 A1).
Regarding claim 1, Kim et al discloses A semiconductor device (fig. 12, fig. 13-13D), comprising:
a fin structure(AF) extending in a first direction disposed over a substrate(310)[0117], the fin structure(AF) including a channel layer(CHR) disposed over an oxide layer(315) fig. 12; a gate electrode layer (420)extending in a second direction over the channel layer(CHR) (fig 13d)[0077][0116], wherein the second direction crosses the first direction fig. 13d/fig.12; wherein the source/drain regions(SR/DR)[0118] include a first epitaxial layer(382), a second epitaxial layer(384), a third epitaxial layer(386), and a fourth epitaxial layer(388) arranged in order in a third direction perpendicular to the first and second directions[0084][0116], wherein the first, second, third, and fourth epitaxial layers(382,384,386,388) have different compositions[0084][0115][0116]; and a dielectric layer(400) [0110]comprising a first portion and a second portion, wherein the first portion is disposed between the oxide layer(315) and the first epitaxial layer(382) along the first direction fig12 and the second portion is disposed over the fourth epitaxial layer(388) fig. 12.
Kim et al fails to teach source/drain regions disposed in the fin structure on opposing sides of the gate electrode layer.
However, Tsai et al discloses a manufacturing method comprising source/drain regions(702) disposed in the fin structure(103) on opposing sides of the gate electrode layer(110[0026][0036][0039] fig. 6/fig. 8. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al with the teachings of Tsai et al to minimize the parasitic resistance[0036].
Regarding claim 3, Kim et al discloses wherein the dielectric layer (400)includes silicon Oxide[0110].
Regarding claim 5, Kim et al discloses , wherein the epitaxial layers include at least one of SiGe, and Ge[0084].
Regarding claim 6,Kim et al discloses further comprising side wall insulating (370)layers[0100] disposed over side walls of the gate electrode layer(420) fig. 13d/fig. 12.
Regarding claim 7, Kim et al discloses wherein the second portion of the dielectric layer(400) is in contact with the side wall insulating layers(370) fig. 12.
Regarding claim 8, Kim et al discloses a semiconductor device, comprising:
a fin (AF)extending in a first direction disposed over a substrate(310)[0117], the fin (AF)including a channel layer (CHR)disposed over an oxide layer(315) [0117] fig. 12; a gate electrode (420)extending in a second direction over the channel layer(CHR) fig. 12/fig. 13, wherein the second direction crosses the first direction fig. 12;
wherein the source/drain regions (SR/DR)include a first layer(382), a second layer(384), a third layer(386), and a fourth layer(388) arranged in order in a third direction perpendicular to the first and second directions fig. 12[0105], wherein the first and second layers(382 & 384) have different compositions, the second and third layers(386 and 388) have different compositions[0105], and the third and fourth layers(386 and 388) have different compositions[0105]; and a first dielectric layer (400)disposed between the oxide layer (315)and the first layer(382), wherein the second layer (384)contacts the first dielectric layer(400), the first layer(382), the channel layer, and the third layer(386) fig. 12.
Kim et al fails to teach source/drain regions disposed in the fin structure on opposing sides of the gate electrode layer.
However, Tsai et al discloses a manufacturing method comprising source/drain regions(702) disposed in the fin structure(103) on opposing sides of the gate electrode layer(110[0026][0036][0039] fig. 6/fig. 8. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al with the teachings of Tsai et al to minimize the parasitic resistance[0036].
,Regarding claim 10, Kim et al discloses wherein the first dielectric layer(400) includes silicon nitride, silicon oxynitride[0110].
Regarding claim 11, Kim et al discloses wherein the first layer(382), second layer(384), third layer(386), and fourth layer (388)include at least one of SiGe, and Ge[0105].
Regarding claim 12, Kim et al discloses further comprising side wall insulating layers(370) disposed over the gate electrode(420)[0101].
Regarding claim 13, Kim yet al discloses wherein a second dielectric layer(410) is disposed over the side wall insulating layers (370)and the fourth layer(388) [0110] fig. 13d.
Regarding claim 14, Kim (fig. 12 et al discloses A semiconductor device, comprising: a fin(AF) extending in a first direction disposed over a substrate(310)[0117], the fin (AF)including a channel(CHR) region disposed over an oxide layer(315)[ [0117] fig. 12; a gate structure (420)extending in a second direction crossing the first direction disposed over the channel region(CHR)fig. 12/fig. 13d; sidewall insulating layers (370)disposed on sidewalls of the gate structure(420)[0101]fig.12/fig. 13d; SiGe source/drain regions(SR/DR-380) disposed in the fin structure (AF)on opposing sides of the channel region(CHR)(fig. 13d[0102][0105], wherein the source/drain regions (SR/DR-380)comprise: a first SiGe layer(382); a second SiGe layer(384) disposed over the first SiGe layer(382); a third SiGe layer(386) disposed over the second SiGe layer(384); and a fourth SiGe layer(388) disposed over the third SiGe layer(386)[0105], wherein the second SiGe layer(384) has a higher Ge concentration than the first SiGe layer(382)[0105], and the third SiGe layer (386)has a higher Ge concentration than the second SiGe layer(384) [0105]; and a dielectric layer (400)made of a different material than the oxide layer(315) comprising a first portion and a second portion(fig.12)[0110],
wherein the first portion contacts the first and second SiGe layers(382/384), and the second portion contacts the fourth SiGe layer(388) and the sidewall insulating layers(370 ) fig. 12.
Kim et al fails to teach source/drain regions disposed in the fin structure on opposing sides the channel region.
However, Tsai et al discloses a manufacturing method comprising source/drain regions(702) disposed in the fin structure(103) on opposing sides of the channel[0026][0036][0039] fig. 6/fig. 8. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al with the teachings of Tsai et al to minimize the parasitic resistance[0036].
Regarding claim 15, Kim et al discloses and further teaches the third SiGe layer(386) having a Ge concentration in a range of 50% to 90% and the fourth SiGe layer (388) having a Ge concentration in a range of 25% to 50%[0105] but fails to teach wherein the third SiGe layer has a higher Ge concentration than the fourth SiGe layer. It would have been obvious to one of ordinary skill in the art before the effective filing date to achieve the third SiGe layer having a higher Ge concentration than the fourth SiGe layer through routine experimentation to optimize the strain in the channel region. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 16, Kim et al discloses , wherein the fourth SiGe layer(388) has a higher Ge concentration than the first SiGe layers(382)[0105].
Regarding claim 17, Kim et al discloses all the claim limitations of claim 15 and further teaches the fourth SiGe layer(388) having a Ge concentration in a range of 25% to 50% and the second SiGe layer (384) having a Ge concentration in a range of 10% to 50%[0105] but fails to teach wherein the fourth SiGe layer has a lower
concentration Ge concentration than the first SiGe layer or the second SiGe layer. It would have been obvious to one of ordinary skill in the art before the effective filing date to achieve fourth SiGe layer having a lower concentration Ge concentration than the second SiGe layer through routine experimentation to optimize the strain in the channel region. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 19, Kim et al discloses wherein the dielectric layer (400)includes silicon nitride, silicon oxynitride[0110].
Regarding claim 20, Kim et al discloses wherein the first portion(400) contacts the oxide layer(315) fig 12.
Claim(s) 1, 3, 5, 6, 7, 8, 10-17, 19, & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2016/0027918 A1-cited in IDS) in view of Ma (US Pub no. 2013/0248948 A1)
Regarding claim 1, Kim et al discloses A semiconductor device (fig. 12, fig. 13-13D), comprising:
a fin structure(AF) extending in a first direction disposed over a substrate(310)[0117], the fin structure(AF) including a channel layer(CHR) disposed over an oxide layer(315) fig. 12; a gate electrode layer (420)extending in a second direction over the channel layer(CHR) (fig 13d)[0077][0116], wherein the second direction crosses the first direction fig. 13d/fig.12; wherein the source/drain regions(SR/DR)[0118] include a first epitaxial layer(382), a second epitaxial layer(384), a third epitaxial layer(386), and a fourth epitaxial layer(388) arranged in order in a third direction perpendicular to the first and second directions[0084][0116], wherein the first, second, third, and fourth epitaxial layers(382,384,386,388) have different compositions[0084][0115][0116]; and a dielectric layer(400) [0110]comprising a first portion and a second portion, wherein the first portion is disposed between the oxide layer(315) and the first epitaxial layer(382) along the first direction fig12 and the second portion is disposed over the fourth epitaxial layer(388) fig. 12.
Kim et al fails to teach source/drain regions disposed in the fin structure on opposing sides of the gate electrode layer.
However, Ma et al discloses a manufacturing method comprising source/drain regions (22)disposed in the fin structure (6) on opposing sides of the gate electrode layer(10)[0040] fig. 1. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al with the teachings of Ma et al to prevent punch through below the channel.
Regarding claim 3, Kim et al discloses wherein the dielectric layer (400)includes silicon Oxide[0110].
Regarding claim 5, Kim et al discloses , wherein the epitaxial layers include at least one of SiGe, and Ge[0084].
Regarding claim 6,Kim et al discloses further comprising side wall insulating (370)layers[0100] disposed over side walls of the gate electrode layer(420) fig. 13d/fig. 12.
Regarding claim 7, Kim et al discloses wherein the second portion of the dielectric layer(400) is in contact with the side wall insulating layers(370) fig. 12.
Regarding claim 8, Kim et al discloses a semiconductor device, comprising:
a fin (AF)extending in a first direction disposed over a substrate(310)[0117], the fin (AF)including a channel layer (CHR)disposed over an oxide layer(315) [0117] fig. 12; a gate electrode (420)extending in a second direction over the channel layer(CHR) fig. 12/fig. 13, wherein the second direction crosses the first direction fig. 12;
wherein the source/drain regions (SR/DR)include a first layer(382), a second layer(384), a third layer(386), and a fourth layer(388) arranged in order in a third direction perpendicular to the first and second directions fig. 12[0105], wherein the first and second layers(382 & 384) have different compositions, the second and third layers(386 and 388) have different compositions[0105], and the third and fourth layers(386 and 388) have different compositions[0105]; and a first dielectric layer (400)disposed between the oxide layer (315)and the first layer(382), wherein the second layer (384)contacts the first dielectric layer(400), the first layer(382), the channel layer, and the third layer(386) fig. 12.
Kim et al fails to teach source/drain regions disposed in the fin structure on opposing sides of the gate electrode layer.
However, Ma et al discloses a manufacturing method comprising source/drain regions(22) disposed in the fin structure (6) on opposing sides of the gate electrode layer(10)[0040] fig. 1. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al with the teachings of Ma et al to prevent punch through below the channel.
,Regarding claim 10, Kim et al discloses wherein the first dielectric layer(400) includes silicon nitride, silicon oxynitride[0110].
Regarding claim 11, Kim et al discloses wherein the first layer(382), second layer(384), third layer(386), and fourth layer (388)include at least one of SiGe, and Ge[0105].
Regarding claim 12, Kim et al discloses further comprising side wall insulating layers(370) disposed over the gate electrode(420)[0101].
Regarding claim 13, Kim yet al discloses wherein a second dielectric layer(410) is disposed over the side wall insulating layers (370)and the fourth layer(388) [0110] fig. 13d.
Regarding claim 14, Kim (fig. 12 et al discloses A semiconductor device, comprising: a fin(AF) extending in a first direction disposed over a substrate(310)[0117], the fin (AF)including a channel(CHR) region disposed over an oxide layer(315)[ [0117] fig. 12; a gate structure (420)extending in a second direction crossing the first direction disposed over the channel region(CHR)fig. 12/fig. 13d; sidewall insulating layers (370)disposed on sidewalls of the gate structure(420)[0101]fig.12/fig. 13d; SiGe source/drain regions(SR/DR-380) disposed in the fin structure (AF)on opposing sides of the channel region(CHR)(fig. 13d[0102][0105], wherein the source/drain regions (SR/DR-380)comprise: a first SiGe layer(382); a second SiGe layer(384) disposed over the first SiGe layer(382); a third SiGe layer(386) disposed over the second SiGe layer(384); and a fourth SiGe layer(388) disposed over the third SiGe layer(386)[0105], wherein the second SiGe layer(384) has a higher Ge concentration than the first SiGe layer(382)[0105], and the third SiGe layer (386)has a higher Ge concentration than the second SiGe layer(384) [0105]; and a dielectric layer (400)made of a different material than the oxide layer(315) comprising a first portion and a second portion(fig.12)[0110],
wherein the first portion contacts the first and second SiGe layers(382/384), and the second portion contacts the fourth SiGe layer(388) and the sidewall insulating layers(370 ) fig. 12.
Kim et al fails to teach source/drain regions disposed in the fin structure on opposing sides of the channel region.
However, Ma et al discloses a manufacturing method comprising source/drain regions(22) disposed in the fin structure (6) on opposing sides of the channel region [0040] fig. 1. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al with the teachings of Ma et al to prevent punch through below the channel.
Regarding claim 15, Kim et al discloses and further teaches the third SiGe layer(386) having a Ge concentration in a range of 50% to 90% and the fourth SiGe layer (388) having a Ge concentration in a range of 25% to 50%[0105] but fails to teach wherein the third SiGe layer has a higher Ge concentration than the fourth SiGe layer. It would have been obvious to one of ordinary skill in the art before the effective filing date to achieve the third SiGe layer having a higher Ge concentration than the fourth SiGe layer through routine experimentation to optimize the strain in the channel region. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 16, Kim et al discloses , wherein the fourth SiGe layer(388) has a higher Ge concentration than the first SiGe layers(382)[0105].
Regarding claim 17, Kim et al discloses all the claim limitations of claim 15 and further teaches the fourth SiGe layer(388) having a Ge concentration in a range of 25% to 50% and the second SiGe layer (384) having a Ge concentration in a range of 10% to 50%[0105] but fails to teach wherein the fourth SiGe layer has a lower
concentration Ge concentration than the first SiGe layer or the second SiGe layer. It would have been obvious to one of ordinary skill in the art before the effective filing date to achieve fourth SiGe layer having a lower concentration Ge concentration than the second SiGe layer through routine experimentation to optimize the strain in the channel region. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 19, Kim et al discloses wherein the dielectric layer (400)includes silicon nitride, silicon oxynitride[0110].
Regarding claim 20, Kim et al discloses wherein the first portion(400) contacts the oxide layer(315) fig 12.
Claim(s) 2 & 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2016/0027918 A1-cited in IDS) in view of Tsai (US Pub no. 2016/0254351 A1) as applied to claim 1 and claim 8 and further in view of Mimura (US Pub no 2003/0168700 A1).
Regarding claim 2, Kim et al as modified by Tsai et al discloses all the claim limitations of claim 1 but fails to teach wherein the oxide layer includes SiGe oxide or Ge oxide.
However, Mimura et al discloses a semiconductor device comprising a buried oxide film (12)of the SiGeO [0116]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al & Tsai et al with the teachings of Mimura et al to reduce interface scattering and improved carrier mobility.
Regarding claim 9, Kim et al discloses all the claim limitations of claim 8 but fails to teach wherein the oxide layer includes SiGe oxide or Ge oxide.
However, Mimura et al discloses a semiconductor device comprising a buried oxide film (12)of the SiGeO [0116]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al with the teachings of Mimura et al to reduce interface scattering and improved carrier mobility.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2016/0027918 A1-cited in IDS) in view of Tsai (US Pub no. 2016/0254351 A1) as applied to claim 1 and further in view of Wang (US Pub no. 2015/0303118 A1).
Regarding claim 4, Kim et al as modified by Tsai et al discloses all the claim limitations of claim 1 but fails to teach wherein a thickness of the dielectric layer is in a range of 1 nm to 10 nm.
However, Wang et al discloses a sub-layer /etch stop layer(154) formed on epitaxial regions (134) having a thickness in a range of 1 nm to 10 nm( between 2.5 nm and 9 nm) [0033]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al & Tsai et al with the teachings of a thickness as taught by Wang et al to optimize etch process.
Claim(s) 2 & 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2016/0027918 A1-cited in IDS) in view of Ma (US Pub no. 2013/0248948 A1) as applied to claim 1 and claim 8 and further in view of Mimura (US Pub no 2003/0168700 A1).
Regarding claim 2, Kim et al as modified by Ma et al discloses all the claim limitations of claim 1 but fails to teach wherein the oxide layer includes SiGe oxide or Ge oxide.
However, Mimura et al discloses a semiconductor device comprising a buried oxide film (12)of the SiGeO [0116]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al & Ma et al with the teachings of Mimura et al to reduce interface scattering and improved carrier mobility.
Regarding claim 9, Kim et al as modified by Ma et al discloses all the claim limitations of claim 8 but fails to teach wherein the oxide layer includes SiGe oxide or Ge oxide.
However, Mimura et al discloses a semiconductor device comprising a buried oxide film (12)of the SiGeO [0116]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al & Ma et al with the teachings of Mimura et al to reduce interface scattering and improved carrier mobility.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub no. 2016/0027918 A1-cited in IDS) in view of Ma (US Pub no. 2013/0248948 A1) as applied to claim 1 and further in view of Wang (US Pub no. 2015/0303118 A1).
Regarding claim 4, Kim et al as modified by Ma et al discloses all the claim limitations of claim 1 but fails to teach wherein a thickness of the dielectric layer is in a range of 1 nm to 10 nm.
However, Wang et al discloses a sub-layer /etch stop layer(154) formed on epitaxial regions (134) having a thickness in a range of 1 nm to 10 nm( between 2.5 nm and 9 nm) [0033]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kim et al & Ma et al with the teachings of a thickness as taught by Wang et al to optimize etch process.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/ Primary Examiner, Art Unit 2813
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