DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Objections
3. Claims 1-8 and 15-20 are objected to because of the following informalities:
Claim 1 recites in line 3 “a potion” which should be changed to “a portion”. Appropriate correction is required.
Claim 15 recites in lines 6-8 “forming a self-aligned etching stop layer on the top surface of the first dielectric layer while a top surface of the blocking layer after forming the blocking layer is exposed” which should be changed to along the lines of “forming a self-aligned etching stop layer on the top surface of the first dielectric layer while a top surface of the blocking layer is exposed” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “the first sidewall of the first etching stop layer is located over and aligned with a sidewall of the second metal line”
The first etching stop layer of the Applicant’s invention, while aligned with a sidewall of the second metal line, is not “over” any of the sidewalls of the second metal line; see for example Applicant’s Fig. 1P element 160 while sharing a sidewall alignment with an element 144 is not “over” it.
For the purposes of compact prosecution, the interpretation will be taken that the current claim requires the first sidewall of the first etching stop layer is aligned with a sidewall of the second metal line in the consideration of prior art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-4 and 8 are rejected under 35 U.S.C. 103 as obvious over Lee et al. (US 2021/0005548 A1), hereinafter as L1, in view of Han et al. (US 2020/0105664 A1), hereinafter as H1
PNG
media_image1.png
869
1048
media_image1.png
Greyscale
6. Regarding Claim 1, L1 discloses an interconnect structure (see Fig. 1A and “Labeled Fig. 1A” above; note elements referred to hereinafter as labeled element and quotations are referencing the labeled figure above), comprising:
a first metal line (labeled element “First Metal Line”, see [0027] “lower wiring structure 210 may include a metal layer 213 and a conductive barrier layer 211”) and a second metal line (labeled element “Second Metal Line”);
a first dielectric layer (labeled element “First Dielectric Layer”, see [0026] “first insulation layer 110”) including a potion between the first metal line and the second metal line (see “Labeled Fig. 1A” above);
a first etching stop layer (labeled element “First Etching Stop Layer”, see [0028] “etch stop layer 310”) on the potion of the first dielectric layer (see “Labeled Fig. 1A” above), wherein a bottom surface of the first etching stop layer is level to a top surface of the first metal line and a top surface of the second metal line (see “Labeled Fig. 1A” above); and
a via (labeled element “Via”, lower portion of 221, 223, see [0023] “upper wiring structure 220”) on the first metal line (see “Labeled Fig. 1A” above).
L1 does not disclose a second etching stop layer including a first portion extending along the top surface of the second metal line, a second portion extending along a first sidewall of the first etching stop layer, and a third portion extending along a top surface of the first etching stop layer
H1 discloses (see Fig. 9) a second etching stop layer (element 230, see [0039] “etch stop structure 230”) including a first portion (portion extending over one of the elements 155) extending along the top surface of the second metal line (element 155, see [0038] “first wiring 155”), a second portion (portion extending along one first sidewall of the element 210) extending along a first sidewall of the first etching stop layer (element 210, see [0037] “insulation pattern 210”), and a third portion (portion extending along a top surface of the element 210) extending along a top surface of the first etching stop layer (see Fig. 9).
The second etching stop layer as taught by H1 is incorporated as a second etching stop layer of L1 (see L1 Fig. 1A on an entire top surfaces and side surfaces of element 310 and extending across top surfaces of element 320 except where the element 220 and 210 are in direct contact in the same manner as H1).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with L1 because the combination allows for added mechanical, chemical, and electrical protection between the surrounding conductive components, and selectivity of material for the added etch stop layer (see H1 Fig. 9 and [0039-0040, 0043]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known interface between stacked interconnects for another in a similar device to obtain predictable results (see H1 Fig. 9).
7. Regarding Claim 2, L1, H1 disclose the interconnect structure as claimed in claim 1, wherein a second sidewall of the first etching stop layer is in direct contact with the via (see H1 Fig. 9).
8. Regarding Claim 3, L1, H1 disclose the interconnect structure as claimed in claim 2, wherein the second sidewall of the first etching stop layer is located over and aligned a sidewall of the first metal line (see H1 Fig. 9).
9. Regarding Claim 4, L1, H1 disclose the interconnect structure as claimed in claim 1, wherein the first sidewall of the first etching stop layer is located over and aligned with a sidewall of the second metal line (see “Labeled Fig. 1A” above).
10. Regarding Claim 8, L1, H1 disclose the interconnect structure as claimed in claim 1, further comprising:
a second dielectric layer (element 120, see [0023] “second insulation layer 120”) over the second etching stop layer and surrounding the via (see “Labeled Fig. 1A”); and
a fourth metal line (element 220L portion of element 220 over the element 221,223 labeled element “Via”) on the via in the second dielectric layer (see “Labeled Fig. 1A”).
11. Claims 5-6 are rejected under 35 U.S.C. 103 as obvious over Lee et al. (US 2021/0005548 A1), hereinafter as L1, in view of Han et al. (US 2020/0105664 A1), hereinafter as H1, in view of Hong et al. (US 2021/0043828 A1), hereinafter as H2
12. Regarding Claim 5, L1, H1 disclose the interconnect structure as claimed in claim 1.
L1, H1 do not disclose further comprising: an encapsulating layer including a first potion interposed between the portion of the first dielectric layer and the first metal line and a second portion between the portion of the first dielectric layer and the second metal line.
H2 discloses further comprising: an encapsulating layer including a first potion interposed between the portion of the first dielectric layer and the first metal line and a second portion between the portion of the first dielectric layer and the second metal line.
H2 discloses (see Fig. 2) an encapsulating layer (element 47, see [0035] “spacers 47 … may
include silicon oxynitride”) lining lower and side surfaces of a second dielectric layer (element 48, see
[0019] “interlayer insulating layers 48”).
The encapsulating layer as taught by H2 is incorporated as an encapsulating layer of L1, H1 (the encapsulating layer element 213 as taught by H2 is combined in L1 see “Labeled Fig. 1A” above to line side and bottom surfaces of first dielectric layer element 110 portions which are separated by elements 210), wherein the combination discloses further comprising: an encapsulating layer including a first potion interposed between the portion of the first dielectric layer and the first metal line and a second portion between the portion of the first dielectric layer and the second metal line (see “Labeled Fig. 1A” above).
It would have been obvious to one having ordinary skill in the art at the time the invention was
effectively filed to incorporate the teachings of H2 with L1, H1 because the combination provides added
mechanical and electrical protection between the physically and electrically protecting conductive
elements, and the combination is simple substitution of one known element for another to obtain
predictable results – simple substitution of one known dielectric structure physically and electrically
protecting embedded conductive elements for another to obtain predictable results (see H2 Fig. 6
elements 47,48 with embedded elements 45).
13. Regarding Claim 6, L1, H1, H2 disclose the interconnect structure as claimed in claim 5, wherein the first etching stop layer overlaps top surfaces of the first portion and the second portion of the encapsulating layer (see “Labeled Fig. 1A” above).
14. Claim 7 is rejected under 35 U.S.C. 103 as obvious over Lee et al. (US 2021/0005548 A1), hereinafter as L1, in view of Han et al. (US 2020/0105664 A1), hereinafter as H1, in view of Hong et al. (US 2021/0043828 A1), hereinafter as H2, in view of Vannier (US 2014/0225278 A1), hereinafter as V1
15. Regarding Claim 7, L1, H1, H2 disclose the interconnect structure as claimed in claim 5, wherein the encapsulating layer further includes a third potion (bottom side portion) under the portion of the first dielectric layer (see H2 Fig. 2).
L1, H1, H2 do not disclose wherein a bottom of the first metal line is lower than a bottom of the third potion of the encapsulating layer.
V1 discloses a recessed interface between stacked conductive interconnects (see Fig. 3 element F1’ and F2’ interface, see [0044] “conductive line F1’” [0047] “conductive line F2’”), having recessed interface between stacked adjacent conductive interconnects (see Fig. 3 between element F1, F2)
The recess at the interface between stacked conductive interconnects as taught by V1 is incorporated as a recess at the interface between stacked conductive interconnects of L1, H1, H2, wherein the combination further discloses wherein a bottom of the first metal line is lower than a bottom of the third potion of the encapsulating layer (see L1 interface between element 210 and 201 is incorporated also at the adjacent labeled element “First Metal Line”, such that a bottom surface of the first metal line interfaces a lower conductive interconnect element 201 to have a lower bottom than that of the third portion of the encapsulating layer which is above the top surface of element 101).
It would have been obvious to one having ordinary skill in the art at the time the invention was
effectively filed to incorporate the teachings of V1 with L1 because the combination provides vertically connected vias for which alignment errors does not present a lateral etch region and unwanted diffusion of conductive material can be prevented, and effects of electromigration are delayed for fewer early fails of the integrated circuit (see Vannier [0049-0050]);
Furthermore, the combination is simple substitution of one known element for another to
obtain predictable results – simple substitution of one known vertical interconnection interface for another to obtain predictable results (see Vannier Fig. 3).
16. Claims 9-10 and 12-13 are rejected under 35 U.S.C. 103 as obvious over Lee et al. (US 2021/0005548 A1), hereinafter as L1, in view of Hong et al. (US 2021/0043828 A1), hereinafter as H2
17. Regarding Claim 9, L1 disclose an interconnect structure (see Fig. 1A and “Labeled Fig. 1A” above; note elements referred to hereinafter as labeled element and quotations are referencing the labeled figure above), comprising:
a first metal line (labeled element “First Metal Line”, see [0027] “lower wiring structure 210 may include a metal layer 213 and a conductive barrier layer 211”) in a first dielectric layer (labeled element “First Dielectric Layer”, see [0026] “first insulation layer 110”);
a first self-aligned etching stop layer (labeled element “First Etching Stop Layer”, see [0028] “etch stop layer 310”; note, the current claim is directed towards a device, and the product-by-process limitations of “self-aligned” do not distinguish from the disclosed prior art structure) on the first dielectric layer (see “Labeled Fig. 1A” above); and
a second dielectric layer (element 120, see [0023] “second insulation layer 120”); and
a via (labeled element “Via”, lower portion of 221, 223, see [0023] “upper wiring structure 220”) in the second dielectric layer (see “Labeled Fig. 1A” above).
L1 does not explicitly disclose an encapsulating layer interposing between the first metal line and the first dielectric layer; a conformal etching stop layer on the first metal line and the first self-aligned etching stop layer, where a first sidewall of the first self-aligned etching stop layer interfaced with the conformal etching stop layer is aligned over a first sidewall of the encapsulating layer interfaced with the first metal line; the second dielectric layer on the conformal etching stop layer
H2 discloses (see Fig. 2) an encapsulating layer (element 47, see [0035] “spacers 47 … may
include silicon oxynitride”) lining lower and side surfaces of a second dielectric layer (element 48, see
[0019] “interlayer insulating layers 48”).
The encapsulating layer as taught by H2 is incorporated as an encapsulating layer of L1, H1 (the encapsulating layer element 213 as taught by H2 is combined in L1 see “Labeled Fig. 1A” above to line side and bottom surfaces of first dielectric layer element 110 portions which are separated by elements 210), wherein the combination discloses an encapsulating layer interposing between the first metal line and the first dielectric layer (see “Labeled Fig. 1A” above).
It would have been obvious to one having ordinary skill in the art at the time the invention was
effectively filed to incorporate the teachings of H2 with L1 because the combination provides added
mechanical and electrical protection between the physically and electrically protecting conductive
elements, and the combination is simple substitution of one known element for another to obtain
predictable results – simple substitution of one known dielectric structure physically and electrically
protecting embedded conductive elements for another to obtain predictable results (see H2 Fig. 6
elements 47,48 with embedded elements 45).
L1, H2 do not disclose a conformal etching stop layer on the first metal line and the first self-aligned etching stop layer, where a first sidewall of the first self-aligned etching stop layer interfaced with the conformal etching stop layer is aligned over a first sidewall of the encapsulating layer interfaced with the first metal line; the second dielectric layer on the conformal etching stop layer
H1 discloses (see Fig. 9) a conformal etching stop layer (element 230, see [0039] “etch stop structure 230”) on the first metal line (first one of the elements 155, see [0038] “first wiring 155”) and the first self-aligned etching stop layer (element 210, see [0037] “insulation pattern 210”), where a first sidewall of the first self-aligned etching stop layer interfaced with the conformal etching stop layer is aligned over a first sidewall of the first metal line (see Fig. 9); the second dielectric layer (element 240, see [0039] “second insulating interlayer 240”) on the conformal etching stop layer (see Fig. 9)
The second etching stop layer as taught by H1 is incorporated as a second etching stop layer of L1 (see L1 Fig. 1A on an entire top surfaces and side surfaces of element 310 and extending across top surfaces of element 320 except where the element 220 and 210 are in direct contact in the same manner as H1), wherein the combination further discloses a first sidewall of the first self-aligned etching stop layer interfaced with the conformal etching stop layer is aligned over a first sidewall of the encapsulating layer interfaced with the first metal line (L1, H2 as combined has a sidewall interfaced between the encapsulating layer and the first metal line).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with L1 because the combination allows for added mechanical, chemical, and electrical protection between the surrounding conductive components, and selectivity of material for the added etch stop layer (see H1 Fig. 9 and [0039-0040, 0043]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known interface between stacked interconnects for another in a similar device to obtain predictable results (see H1 Fig. 9).
18. Regarding Claim 10, L1, H2, H1 disclose the interconnect structure as claimed in claim 9, further comprising (see L1):
a second metal line (labeled element “Second Metal Line”) in the first dielectric layer and in contact with the via (see “Labeled Fig. 1A” above), wherein a second sidewall of the first self-aligned etching stop layer interfaced with the via is aligned over a second sidewall of the encapsulating layer interfaced with the second metal line (see “Labeled Fig. 1A” above, the combined encapsulating layer is on sides and bottom surfaces of each of the element 110 portions, such that the other of the two sides interfacing the second metal line is vertically aligned with the second sidewall of the first self-aligned etching stop layer interfaced with the via).
19. Regarding Claim 12, L1, H2, H1 disclose the interconnect structure as claimed in claim 9, wherein a dielectric constant of the conformal etching stop layer is greater than a dielectric constant of the second dielectric layer (see L1 [0026] “the first insulation layer 110 may include a low dielectric layer (for example, a SiOC layer or a SiCOH layer) having a low dielectric constant of about 2.2 to about 3.0” and see H2 [0040] “etch stop layer 232 may include, e.g. aluminum oxide …” which has a higher dielectric constant than the low dielectric constant SiOC).
20. Regarding Claim 13, L1, H2, H1 disclose the interconnect structure as claimed in claim 9.
L1, H2, H1 as previously combined do not disclose wherein the via is interfaced with a top surface of the first self-aligned etching stop layer.
H1 further discloses wherein the via is interfaced with a top surface of the first self-aligned etching stop layer (see Fig. 14 the via element 280 is offset such that it is interfaced with a top surface of element 210).
The alignment of the via as taught by H1 is incorporated as the alignment of the via of L1.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of H1 with L1 because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known via alignment for another for which the two are provided as known alternatives (see H1 Figs. 1-10 versus Figs. 12-14 and [0055])
Allowable Subject Matter
21. Claims 15-20 would be allowable if rewritten to overcome the objected informalities
Claims 11 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reason for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
22. Claim 11, “a second self-aligned etching stop layer under the first metal line and the encapsulating layer, wherein a bottom portion of the second metal line is surrounded by the second self-aligned etching stop layer” – as instantly claimed and in combination with the additionally claimed limitations.
23. Claim 14, “a blocking layer between the first metal line and the conformal etching stop layer, wherein the blocking layer includes an organic sulfur compound, an organic phosphor compound, or an organic silicon compound” – as instantly claimed and in combination with the additionally claimed limitations.
24. Claim 15, “forming a blocking layer on top surfaces of the first metal line and the second metal line while a top surface of the first dielectric layer is exposed; forming a self-aligned etching stop layer on the top surface of the first dielectric layer while a top surface of the blocking layer after forming the blocking layer is exposed; removing the blocking layer to expose the top surfaces of the first metal line and the second metal line; forming a conformal etching stop layer along the top surface of the first metal line and the second metal line and sidewalls and a top surface of the self-aligned etching stop layer; and forming a second dielectric layer on the conformal etching stop layer” – as instantly claimed and in combination with the additionally claimed limitations.
All claims depending on the current claim incorporate the same allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMUEL PARK/Examiner, Art Unit 2818
Prosecution Insights