DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
It has been acknowledged that the applicant has elected without traverse Invention (Group I, claims 1-12) by cancelling claims 13-20 (Group II), and in addition added new claims 21-28 per the response dated on 6/17/2026. Currently claims 1-12 and 21-28 are present for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/21/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “DIE EDGE STRUCTURE FOR MOLDING COMPOUND FILLING AND THE METHODS OF FORMING THE SAME WHICH INCLUDE A LASER GROOVING PROCESS FOR FORMING TRENCHES WITH ROUNDED CORNER REGIONS”.
Claim Objections
Claims 1, 3-4, and 10 are objected, because the following limitations/phrases should be aligned to the prior limitations/phrases to avoid 112 issues due to indefiniteness:
Claim 1: “increasing” on line 10 should be changed to “increasingly”.
Claim 3: “the top surface” on line 1 should be changed to “the top surface of the corner region”.
Claim 4: “the second dielectric layer” on line 2 and on line 3 should be changed to “the second dielectric layer of the wafer”.
Claim 10: “the second dielectric layer” on lines 6-7 should be changed to “the second dielectric layer of the wafer”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 21-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, claim 9 recites the limitation “the plurality of dies” in line 2. There is insufficient antecedent basis for this limitation in claim 9 and claim 1 on which claim 9 depends. For examining purpose, claim 9 is considered to be dependent on claim 8, which recites “a plurality of dies”.
Regarding claim 21, it is not clear what is implied by the term “respective” on line 10. For examining purpose, “respective portions” is considered to be “remaining portions”.
Regarding claims 22-28, these claims are rejected because they depend on claim 21.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 10-12 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of co-pending Application No. 19/713,956 (will be referred as Application-956). Although the claims at issue are not identical, they are not patentably distinct from each other as explained below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application – 18/657,170
US Pat. Application - 19/713,956 (will be referred as Application-956)
Claim 10:
A method comprising:
forming a wafer;
etching a first dielectric layer of the wafer to form a first trench between two dies of the wafer, wherein a first portion of a second dielectric layer of the wafer is directly underlying the first trench; and
performing a laser grooving process to remove the first portion of the second dielectric layer and to form a second trench,
wherein the laser grooving process is performed using picosecond laser beams.
Claim 1:
A method comprising:
forming a wafer;
etching a first dielectric layer of the wafer to form a first trench between two dies of the wafer, wherein a middle portion of a second dielectric layer of the wafer is directly underlying the first trench;
performing a laser grooving process to remove the middle portion of the second dielectric layer of the wafer, wherein a second trench is formed in the second dielectric layer, and is underlying and joined to the first trench,
wherein the laser grooving process results in the second dielectric layer to comprise a top surface, a sidewall, and a corner surface facing the second trench, and wherein the corner surface connects the top surface to the sidewall; and
sawing the wafer to separate the two dies of the wafer from each other.
Claim 2:
The method of claim 1.
wherein the laser grooving process is performed using picosecond laser beams.
Claim 12:
The method of claim 10 further comprising
sawing the wafer through the second trench, wherein the wafer is separated into a plurality of dies.
Claim 1 last line (see above):
sawing the wafer to separate the two dies of the wafer from each other.
Regarding claim 10, Claim 2 of Application-956 teaches all the limitations of claim 10, as mapped in the table above. However, there are some differences. The portion of the second dielectric layer which is removed by the laser grooving process is “the middle portion of the second dielectric layer” in Application-956 instead of “the first portion of the second dielectric layer” in the current application, and therefore is more specific in terms of the location of the portion in the second dielectric layer. Accordingly, claim 2 teaches all the limitations of claim 10 of the current application.
Regarding claim 12, claim 2 teaches all limitations of claim 10, and claim 1 further teaches the limitations of claim 12, as it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the sawing process to separate the dies would be performed through the second trench in claim 1 of Application-956.
Claim 11 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of co-pending Application No. 19/713,956 (will be referred as Application-956) as applied to claims 10 and 12 above, and further in view of Abelo (US 2007/0272668 A1).
This is a provisional nonstatutory double patenting rejection.
Instant Application – 18/657,170
US Pat. Application - 19/713,956 (will be referred as Application-956)
Claim 10:
A method comprising:
forming a wafer;
etching a first dielectric layer of the wafer to form a first trench between two dies of the wafer, wherein a first portion of a second dielectric layer of the wafer is directly underlying the first trench; and
performing a laser grooving process to remove the first portion of the second dielectric layer and to form a second trench,
wherein the laser grooving process is performed using picosecond laser beams.
Claim 1:
A method comprising:
forming a wafer;
etching a first dielectric layer of the wafer to form a first trench between two dies of the wafer, wherein a middle portion of a second dielectric layer of the wafer is directly underlying the first trench;
performing a laser grooving process to remove the middle portion of the second dielectric layer of the wafer, wherein a second trench is formed in the second dielectric layer, and is underlying and joined to the first trench,
wherein the laser grooving process results in the second dielectric layer to comprise a top surface, a sidewall, and a corner surface facing the second trench, and wherein the corner surface connects the top surface to the sidewall; and
sawing the wafer to separate the two dies of the wafer from each other.
Claim 11:
The method of claim 10,
wherein a surface of the wafer formed by the laser grooving process is rounded.
Claim 8:
The method of claim 1,
wherein the corner surface is continuously curved in a direction pointing from the top surface to the sidewall.
Regarding claim 11, Claim 8 of Application-956 teaches all the limitations of claim 11, except that
the laser grooving process is performed using picosecond laser beams.
Abelo, on the other hand, teaches a laser grooving method for forming grooves (streets 214, Fig. 2A, [0035]) by a laser beam (laser beam 216, Fig. 2A, [0035]), wherein the laser grooving process is performed using picosecond laser beams ([0037]: “the pulse width is set in a range between approximately 1 picosecond and approximately 10 picoseconds.”).
Using picosecond laser beams is common in laser grooving processes in semiconductor manufacturing for forming grooves, as also evidenced by Jeong (US 2021/0407854 A1, Fig. 7, [0097]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to perform the laser grooving process of claim 8 of Application-956 by using the picosecond laser beams as taught by Abelo to obtain the predictable result of forming grooves that are suitable for dividing the semiconductor wafer into individual device dies (see MPEP 2143(I)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 21 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Topacio (US 2017/0301638 A1).
Regarding claim 21, Topacio teaches a method ([0029]) comprising:
forming a wafer (silicon wafer, Fig. 6, [0016]-[0017]));
sawing (Fig. 12: using dicing saw 282, [0038]) the wafer (semiconductor workpiece 200, Fig. 12, [0038]) to form a plurality of device dies (semiconductor chip 205 and semiconductor chip 210, Fig. 12, [0038]: “the semiconductor workpiece 200 may undergo a singulation process to singulate the semiconductor chips 205 and 210”), wherein a device die (semiconductor chip 205 or semiconductor chip 210, Fig. 12) of the plurality of device dies (semiconductor chip 205 and semiconductor chip 210, Fig. 12: while Topacio did not show individual dies after separation in a figure, a person of ordinary skill in the art before the effective filing date of the claimed invention would deduct this structure from Fig. 12, as shown in Illustrative Fig. 1 which is a cut and upside-down version of Fig. 12) comprises:
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a semiconductor substrate (comprising semiconductor workpiece 200 and circuit structure 220 (see Fig. 11 for the labels), see substrate as labeled Illustrative Fig. 1, [0034]: “The semiconductor workpiece 200 includes multiple semiconductor chips”) comprising a first edge (first edge, Illustrative Fig. 1);
a first dielectric layer (passivation structure 230 (see Fig. 11 for the label), shown as first dielectric layer in Illustrative Fig. 1, [0034]: “passivation structure 230 … may consist of a single or multiple layers of dielectric materials, such as silicon dioxide and silicon nitride”) underlying the semiconductor substrate (substrate, Illustrative Fig. 1), wherein the first dielectric layer (first dielectric layer, Illustrative Fig. 1) comprises:
a bottom surface (bottom surface, Illustrative Fig. 1); and
a corner surface (corner surface, Illustrative Fig. 1) connecting the bottom surface (bottom surface, Illustrative Fig. 1) to the first edge (first edge, Illustrative Fig. 1), wherein portions of the corner surface (the vertical portion of the corner surface, Illustrative Fig. 1) closer to the first edge (first edge, Illustrative Fig. 1) are increasingly higher than respective portions of the corner surface (horizontal portion of the corner surface, Illustrative Fig. 1) closer to the bottom surface (bottom surface, Illustrative Fig. 1); and
a second dielectric layer (polymer 235 (see Fig. 11 for the label), shown as second dielectric layer in Illustrative Fig. 1, [0034]: “The polymer layer 235 may be composed of polyimide” which is a dielectric material) underlying and contacting the first dielectric layer (first dielectric layer, Illustrative Fig. 1), wherein the second dielectric layer (second dielectric layer, Illustrative Fig. 1) comprises a second edge (second edge, Illustrative Fig. 1) laterally recessed from the first edge (first edge, Illustrative Fig. 1).
Regarding claim 25, Topacio teaches the method of claim 21, wherein the corner surface (corner surface, Illustrative Fig. 1) has a lateral length (horizontal length as defined to be equal to the thickness of the first dielectric layer, Illustrative Fig. 1: there is no specific limitation on how the corner surface is defined) and a vertical length (vertical length equal to the thickness of the first dielectric layer, Illustrative Fig. 1: there is no specific limitation on how the corner surface is defined) having a difference smaller than about 20 percent of both of the lateral length and the vertical length (0% as both length are equal).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Topacio (US 2017/0301638 A1) in view of Kurosawa (US 2005/0006725 A1).
Regarding claim 1, Topacio teaches a method ([0029]) comprising:
forming a wafer (silicon wafer, Fig. 6, [0016]-[0017]);
etching a first dielectric layer (polymer 235, Fig. 6, [0034]: “The polymer layer 235 may be composed of polyimide” which is a dielectric material) of the wafer (silicon wafer, Fig. 6) to form a first trench (opening 245, Fig. 6, [0034]: “the openings 240, 245 and 250 may be formed by an etching process in which a suitable mask (not shown) is formed on the polymer film 235 and an etch process is used to cut the openings 240, 245 and 250.”) between two dies (semiconductor chip 205 and semiconductor chip 210, Fig. 6, [0038]) of the wafer (silicon wafer, Fig. 6), wherein a first portion (the portion overlapping the dicing street 215, Fig. 6, [0235]) of a second dielectric layer (passivation structure 230, Fig. 6, [0034]: “passivation structure 230 … may consist of a single or multiple layers of dielectric materials, such as silicon dioxide and silicon nitride”) of the wafer (silicon wafer, Fig. 6) is directly underlying the first trench (opening 245, Fig. 6); and
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performing a laser grooving process (Fig. 11, [0038]: ”a laser source 276 may be used to cut a trench 277”) to remove the first portion (the portion overlapping the dicing street 215, Fig. 11) of the second dielectric layer (passivation structure 230, Fig. 11) of the wafer (silicon wafer, Fig. 11), wherein a second trench (trench 277, Fig. 11, [0038]) is formed, and is underlying and joined to the first trench (opening 245, Fig. 11), wherein the second dielectric layer (passivation structure 230, Fig. 11) comprises a corner region (see the corner region is labeled Illustrative Fig. 2, which is annotated version of Fig. 11) where the first trench (opening 245, Illustrative Fig. 2) is joined to the second trench (trench 277, Illustrative Fig. 2).
Topacio, however, does not teach that portions of a top surface of the corner region closer to a center middle line of the second trench are increasing lower than respective portions of the top surface of the corner region farther away from the center middle line.
Kurosawa, on the other hand, teaches a method for dividing a semiconductor wafer (Figs. 12-13) along trenches (groove Gr, Fig. 12-13, [0059]) to isolate individual chips (semiconductor chips 1, Fig. 12-13, [0059]), wherein the grooves (groove Gr, Fig. 12-14) have curved corners (Figs. 12-14, [0061]). Kurosawa further discloses that chipping of the semiconductor chips during breaking or dicing can be reduced by rounded corners ([0048]: “As shown in FIG. 2, depths of flaws (crushed layer) ΔD1 and ΔD2 caused to the semiconductor chip 1 in a dicing process are about 0.5 µm. Therefore, an influence of damages due to chipping can be reduced by processing the portion of the semiconductor chip 1 where the side surfaces 1SA to 1SD and the rear surface IRS cross into a shape having a curvature radius of at least 0.5 µm”).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include steps in the method of Topacio to round the corner region as taught by Kurosawa to minimize the chipping of the dies. Thus, the combination of Topacio and Kurosawa leads to a structure where the corner region (Illustrative Fig. 2) is rounded, which results in that
portions of a top surface of the corner region closer to a center middle line of the second trench are increasing lower than respective portions of the top surface of the corner region farther away from the center middle line.
Regarding claim 8, Topacio in view of Kurosawa teaches the method of claim 1, wherein
Topacio also teaches that the method further comprises sawing (Fig. 12: using dicing saw 282, [0038]) the wafer (Fig. 12, [0038]) through the second trench (trench 277, Fig. 12), wherein the wafer (the semiconductor workpiece 200, Fig. 12, [0038]) is separated into a plurality of dies (semiconductor chip 205 and semiconductor chip 210, Fig. 12, [0038]: “the semiconductor workpiece 200 may undergo a singulation process to singulate the semiconductor chips 205 and 210”).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Topacio (US 2017/0301638 A1) in view of Kurosawa (US 2005/0006725 A1) as applied to claims 1 and 8 above, and further in view of Abelo (US 2007/0272668A1).
Regarding claim 2, while Topacio in view of Kurosawa teaches the method of claim 1,
neither Topacio nor Kurosawa discloses the details of the laser and therefore do not teach that the laser grooving process is performed using picosecond laser beams.
Abelo, on the other hand, teaches a laser grooving method for forming grooves (streets 214, Fig. 2A, [0035]) by a laser beam (laser beam 216, Fig. 2A, [0035]), wherein the laser grooving process is performed using picosecond laser beams ([0037]: “the pulse width is set in a range between approximately 1 picosecond and approximately 10 picoseconds.”).
Using picosecond laser beams is common in laser grooving processes in semiconductor manufacturing for forming grooves, as also evidenced by Jeong (US 2021/0407854 A1, Fig. 7, [0097]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to perform the laser grooving process of Topacio in view of Kurosawa by using the picosecond laser beams as taught by Abelo to obtain the predictable result of forming groves that are suitable for dividing the semiconductor wafer into individual device dies (see MPEP 2143(I)).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Topacio (US 2017/0301638 A1) in view of Kurosawa (US 2005/0006725 A1) as applied to claims 1 and 8 above, and further in view of Mohammed (US 2011/0155435 A1).
Regarding claim 3, while Topacio in view of Kurosawa teaches the method of claim 1,
neither Topacio nor Kurosawa teaches that the top surface has a roughness smaller than about 1.5 µm.
Mohamed, on the other hand, teaches a method for dicing wafers (Figs. 11A-B, [0022]) using a picosecond laser wherein a surface roughness of 0.2 µm could be obtained ([0022]).
Mohammed further discloses that pulse duration is a strong factor to control surface roughness, and much smoother surface may be achieved with femto-second lasers. ([0022]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use a picosecond or femtosecond laser for laser grooving process to obtain a smooth surface that is acceptable for dicing (Mohamed, [0022] and claim 6). Thus, the combination of Topacio, Kurosawa and Mohamed meets the limitation that the top surface has a roughness smaller than about 1.5 µm.
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Topacio (US 2017/0301638 A1) in view of Kurosawa (US 2005/0006725 A1) as applied to claims 1 and 8 above, and further in view of Kumazawa (US 2020/0185276 A1).
Regarding claim 4, while Topacio in view of Kurosawa teaches the method of claim 1,
neither Topacio nor Kurosawa teaches that in the laser grooving process, more laser pulses are projected onto portions of the second dielectric layer closer to the center middle line than portions of the second dielectric layer farther away from the center middle line.
Kumazawa, on the other hand, teaches a method for laser grooving (laser processed grooves 7-3, Figs. 25, [0106]) wherein in the laser grooving process (Fig. 25), more laser pulses (pulsed laser beam 41, Fig. 25, [0110]) are projected onto portions of the substrate (substrate 2, Fig. 25, [0051]: while the substrate in the method of Kumazawa is not purely a dielectric material, the method of Kumazawa can also be applied to other material as discussed below) closer to the center middle line than portions of the substrate farther away from the center middle line (Fig. 25, [0110]: “the laser processing apparatus 40 applies the pulsed laser beam 41 along the longitudinal direction of each division line 3 while scanning the laser beam 41 in the width direction 45 of each division line 3, to form the laser processed grooves 7-3 along the division lines 3. In this instance, the pulses of the laser beam 41 are applied in the largest number to the center in the width direction of each division line 3, and the number of pulses of the laser beam 41 to be applied is decreased toward outer sides in the width direction of each division line 3. For this reason, in the laser processing step ST15 in the third embodiment, the sectionally V-shaped laser processed grooves 7-3 each becoming shallower toward the outer sides in the width direction of each division line 3 are formed.”).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that Topacio in view of Kurasawa also uses a laser grooving method (Fig. 11, [0038]: ”a laser source 276 may be used to cut a trench 277”) to form the grooves (trench 277, Fig. 11), and the laser grooving method of Kumazawa can be applied to any material that can be etched or ablated by a laser beam. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Topacio in view of Kurosawa according to the teachings of Kumazawa to form the curved or sloped top surface (see claim 1, where the top surface is increasingly lower towards centerline) during the formation of the grooves by projecting more laser pulses onto portions of the second dielectric layer closer to the center middle line than portions of the second dielectric layer farther away from the center middle line, which would provide advantages over alternative methods (chemical or mechanical) for shaping the curved top surface, because no extra equipment would be required, and potential interference of alternative methods with device processing can be avoided.
Thus, the combination of Topacio, Kurosawa, and Kumazawa meets all the limitations of claim 4.
Regarding claim 5, while Topacio in view of Kurosawa teaches the method of claim 1,
neither Topacio nor Kurosawa teaches that in the laser grooving process, laser pulses are projected on a region between a first point farther away from the center middle line and a second point closer to the center middle line, and wherein from the first point to the second point, numbers of laser pulses increase gradually.
Kumazawa, on the other hand, teaches a method for laser grooving (laser processed grooves 7-3, Figs. 25, [0106]) wherein in the laser grooving process (Fig. 25), more laser pulses (pulsed laser beam 41, Fig. 25, [0110]) are projected between a first point farther away from the center middle line and a second point closer to the center middle line, and wherein from the first point to the second point, numbers of laser pulses increase gradually (Fig. 25, [0110]: “the laser processing apparatus 40 applies the pulsed laser beam 41 along the longitudinal direction of each division line 3 while scanning the laser beam 41 in the width direction 45 of each division line 3, to form the laser processed grooves 7-3 along the division lines 3. In this instance, the pulses of the laser beam 41 are applied in the largest number to the center in the width direction of each division line 3, and the number of pulses of the laser beam 41 to be applied is decreased toward outer sides in the width direction of each division line 3. For this reason, in the laser processing step ST15 in the third embodiment, the sectionally V-shaped laser processed grooves 7-3 each becoming shallower toward the outer sides in the width direction of each division line 3 are formed.”, where the first point is the edge of the shaped structure and the second point is the center line.).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that Topacio in view of Kurasawa also uses a laser grooving method (Fig. 11, [0038]: ”a laser source 276 may be used to cut a trench 277”) to form the grooves (trench 277, Fig. 11), and the laser grooving method of Kumazawa can be applied to any material that can be etched or ablated by a laser beam. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Topacio in view of Kurosawa according to the teachings of Kumazawa to form the curved or sloped top surface (see claim 1, where the top surface is increasingly lower towards centerline) during the formation of the grooves by projecting laser pulses on a region between a first point farther away from the center middle line (the first point being the position on the top surface where the curving starts) and a second point closer to the center middle line (the second point being any point towards the center line at a location before the curving ends), and wherein from the first point to the second point, numbers of laser pulses increase gradually, which would provide advantages over alternative methods (chemical or mechanical) for shaping the curved top surface, because no extra equipment would be required, and potential interference of alternative methods with device processing can be avoided.
Thus, the combination of Topacio, Kurosawa, and Kumazawa meets all the limitations of claim 5.
Regarding claim 6, while Topacio in views of Kurosawa, and Kumazawa teaches the method of claim 5,
Topacio, Kurosawa, and Kumazawa do not teach that from the first point to the second point, the numbers of laser pulses increase linearly.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would know that the etch/ablation rate in dielectric materials depends on wavelength of the laser, the dielectric material, and the duration and frequency of pulses as evidenced by Ehrhardt (Figs. 2 and 4; Ehrhardt et al., Microstructuring of fused silica by laser-induced backside wet etching using picosecond laser pulses, Applied Surface Science, Volume 256, Issue 23, 2010, Pages 7222-7227, doi.org/10.1016/j.apsusc.2010.05.055.) and Kautek (Figs. 1-2; Kautek et al., Appl. Phys. Lett. 69, 3146–3148 (1996), https://doi.org/10.1063/1.116810), and these parameters can be chosen so that the etch rate is linearly dependent of the number of pulses (see Figs. 1-2 of Kautek), which would provide the benefit of determining the number of pulses peer location according to curvature at that location. Accordingly. For a first point and second point on a piecewise linear region of the top surface, the numbers of laser pulses increase linearly from the first point to the second point.
Regarding claim 7, while Topacio in views of Kurosawa, and Kumazawa teaches the method of claim 5,
Topacio, Kurosawa, and Kumazawa do not teach that from the first point to the second point, the numbers of laser pulses increase exponentially.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would know that the etch/ablation rate in dielectric materials depends on wavelength of the laser, the dielectric material, and the duration and frequency of pulses as evidenced by Ehrhardt (Figs. 2 and 4; Ehrhardt et al., Microstructuring of fused silica by laser-induced backside wet etching using picosecond laser pulses, Applied Surface Science, Volume 256, Issue 23, 2010, Pages 7222-7227, doi.org/10.1016/j.apsusc.2010.05.055.) and Kautek (Figs. 1-2; Kautek et al., Appl. Phys. Lett. 69, 3146–3148 (1996), https://doi.org/10.1063/1.116810), and these parameters can be chosen so that the etch rate is linearly dependent of the number of pulses (see Figs. 1-2 of Kautek), which would provide the benefit of determining the number of pulses peer location according to curvature at that location. Accordingly, for a first point and second point on a piecewise exponential curvature region of the top surface, the numbers of laser pulses increase exponentially from the first point to the second point.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Topacio (US 2017/0301638 A1) in view of Kurosawa (US 2005/0006725 A1) as applied to claims 1 and 8 above, and further in view of Chang (US 2020/0350209 A1).
Regarding claim 9, while Topacio in view of Kurosawa teaches the method of (see 35. U.S.C. 112(b) rejection above)
neither Topacio nor Kurosawa teaches that the method further comprises:
bonding a die in the plurality of dies to a package component; and
molding the die in a molding compound, wherein the molding compound is filled into the first trench.
Chang, on the other hand, teaches a method for forming a semiconductor device package (Figs. 6A-B, [0006]), wherein the method comprises dicing a wafer (wafer 200, Figs. 2-5, [0021]) to isolate a plurality of dies (die 100, Figs 2-5, [0021]) from each other,
bonding a die (die 100, Figs. 6A-B, [0031]-[0032]) in the plurality of dies (die 100, Figs 2-5) to a package component (device package 300, Figs. 6A-B); and
molding the die (Figs. 6A-B, [0032]) in a molding compound (encapsulant 304, Figs. 6A-B, [0033]: “Encapsulant 304 may comprise a molding compound”), wherein the molding compound (encapsulant 304, Figs. 6A-B) is filled into the first trench (region corresponding to material of recast region 208, Fig. 6B: this region was a trench formed as a trench (see Figs. 4-5).
Chang further discloses that the method of forming a package as disclosed by Chang provides improvement in integration density, which allows more components to be integrated into a given area ([0002]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to integrate the method disclosed by Chang with the method of Topacio in view of Kurosawa to manufacture semiconductor packages with a high packing density and small footprint (Chang, [0002]).
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Topacio (US 2017/0301638 A1) in view of Abelo (US 2007/0272668A1).
Regarding claim 10, Topacio teaches a method ([0029]) comprising:
forming a wafer (silicon wafer, Fig. 6, [0016]-[0017]);
etching a first dielectric layer (polymer 235, Fig. 6, [0034]: “The polymer layer 235 may be composed of polyimide” which is a dielectric material) of the wafer (silicon wafer, Fig. 6) to form a first trench (opening 245, Fig. 6, [0034]: “the openings 240, 245 and 250 may be formed by an etching process in which a suitable mask (not shown) is formed on the polymer film 235 and an etch process is used to cut the openings 240, 245 and 250.”) between two dies (semiconductor chip 205 and semiconductor chip 210, Fig. 6, [0038]) of the wafer (silicon wafer, Fig. 6), wherein a first portion (the portion overlapping the dicing street 215, Fig. 6, [0235) of a second dielectric layer (passivation structure 230, Fig. 6, [0034]: “passivation structure 230 … may consist of a single or multiple layers of dielectric materials, such as silicon dioxide and silicon nitride”) of the wafer (silicon wafer, Fig. 6) is directly underlying the first trench (opening 245, Fig. 6); and
performing a laser grooving process (Fig. 11, [0038]: ”a laser source 276 may be used to cut a trench 277”) to remove the first portion (the portion overlapping the dicing street 215, Fig. 11) of the second dielectric layer (passivation structure 230, Fig. 11) and to form a second trench (trench 277, Fig. 11, [0038]).
Topacio, however, does not teach that
the laser grooving process is performed using picosecond laser beams.
Abelo, on the other hand, teaches a laser grooving method for forming grooves (streets 214, Fig. 2A, [0035]) by a laser beam (laser beam 216, Fig. 2A, [0035]), wherein
the laser grooving process is performed using picosecond laser beams ([0037]: “the pulse width is set in a range between approximately 1 picosecond and approximately 10 picoseconds.”).
Using picosecond laser beams is common in laser grooving processes in semiconductor manufacturing for forming grooves, as also evidenced by Jeong (US 2021/0407854 A1, Fig. 7, [0097]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to perform the laser grooving process of Topacio by using the picosecond laser beams as taught by Abelo to obtain the predictable result of forming groves that are suitable for dividing the semiconductor wafer into individual device dies (see MPEP 2143(I)).
Regarding claim 12, Topacio in view of Abelo teaches the method of claim 10, wherein
Topacio also teaches that the method further comprises sawing (Fig. 12: using dicing saw 282, [0038]) the wafer (Fig. 12, [0038]) through the second trench (trench 277, Fig. 12), wherein the wafer (the semiconductor workpiece 200, Fig. 12, [0038]) is separated into a plurality of dies (semiconductor chip 205 and semiconductor chip 210, Fig. 12, [0038]: “the semiconductor workpiece 200 may undergo a singulation process to singulate the semiconductor chips 205 and 210”).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Topacio (US 2017/0301638 A1) in view of Abelo (US 2007/0272668A1) as applied to claims 10 and 12 above, and further in view of Kurosawa (US 2005/0006725 A1).
Regarding claim 11, while Topacio in view of Abelo teaches the method of claim 10,
neither Topacio nor Abelo teaches that a surface of the wafer formed by the laser grooving process is rounded.
Kurosawa, on the other hand, teaches a method for dividing a semiconductor wafer (Figs. 12-13) along trenches (groove Gr, Fig. 12-13, [0059]) to isolate individual chips (semiconductor chips 1, Fig. 12-13, [0059]), wherein the grooves (groove Gr, Fig. 12-14) have curved corners (Figs. 12-14, [0061]). Kurosawa further discloses that chipping of the semiconductor chips during breaking or dicing can be reduced by rounded corners ([0048]: “As shown in FIG. 2, depths of flaws (crushed layer) ΔD1 and ΔD2 caused to the semiconductor chip 1 in a dicing process are about 0.5 µm. Therefore, an influence of damages due to chipping can be reduced by processing the portion of the semiconductor chip 1 where the side surfaces 1SA to 1SD and the rear surface IRS cross into a shape having a curvature radius of at least 0.5 µm”).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Topacio in view of Abelo to shape the surface of the wafer formed by the laser grooving process rounded at the corner of the second dielectric layer of the wafer, to obtain the benefit of minimizing the chipping of the dies. Thus, the combination of Topacio, Abelo, and Kurosawa meets all the limitations of claim 11.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Topacio (US 2017/0301638 A1) as applied to claims 21 and 25 above, and further in views of Kurosawa (US 2005/0006725 A1) and Park (KR 100663000 B1).
Regarding claim 22, while Topacio teaches the method of claim 21,
Topacio does not teach that the method further comprises using a laser beam to round the corner surface.
Kurosawa, on the other hand, teaches a method for dividing a semiconductor wafer (Figs. 12-13) along trenches (groove Gr, Fig. 12-13, [0059]) to isolate individual chips (semiconductor chips 1, Fig. 12-13, [0059]), wherein the trenches (groove Gr, Fig. 12-14) have round corner surface (Figs. 12-14, [0061]).
Kurosawa further discloses that chipping of the semiconductor chips during breaking or dicing can be reduced by rounded corners ([0048]: “As shown in FIG. 2, depths of flaws (crushed layer) ΔD1 and ΔD2 caused to the semiconductor chip 1 in a dicing process are about 0.5 µm. Therefore, an influence of damages due to chipping can be reduced by processing the portion of the semiconductor chip 1 where the side surfaces 1SA to 1SD and the rear surface IRS cross into a shape having a curvature radius of at least 0.5 µm”). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include steps in the method of Topacio to round the corner surface as taught by Kurosawa to minimize the chipping of the dies during dicing. Thus, combination of Topacio and Kurosawa leads to a method comprising rounding the corner surface.
Neither Topacio nor Kurosawa, however, teaches that the method comprises using a laser beam to round the corner surface.
Park, on the other hand, teaches a method (Fig. 3; page 3, last three paragraphs) where the corners of a trench (trench 14, Fig. 3, third paragraph from the bottom) are rounded by a laser beam (page 3: the laser beam is scanned multiple times from different directions).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that Topacio also utilizes a laser grooving method (Fig. 11, [0038]: ”a laser source 276 may be used to cut a trench 277”) to form grooves (trench 277, Fig. 11), where the edges of the grooves forms the corner surface (Fig. 11 and Illustrative Fig. 1) of Topacio. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Topacio according to the teachings of Park to use a laser beam for both forming the trench and rounding the edges which would provide advantages over alternative methods (chemical or mechanical) for rounding the corners because no extra equipment would be required, and potential interference of alternative methods with device processing can be avoided.
Thus, the combination of Topacio, Kurosawa, and Park meets all the limitations of claim 22.
Regarding claim 23, teaches the method of claim 21 further comprising using a laser beam to shape the corner surface as being straight and rounded.
Topacio does not teach that the method further comprises using a laser beam to shape the corner surface as being straight and rounded.
Kurosawa, on the other hand, teaches a method for dividing a semiconductor wafer (Figs. 12-13) along trenches (groove Gr, Fig. 12-13, [0059]) to isolate individual chips (semiconductor chips 1, Fig. 12-13, [0059]), wherein trenches (groove Gr, Fig. 12-14) have corner surfaces (Figs. 12-14, [0061]) as being straight and rounded (see Fig. 14, where the corner region has both rounded and straight surfaces).
Kurosawa further discloses that chipping of the semiconductor chips during breaking or dicing can be reduced by rounded corners ([0048]: “As shown in FIG. 2, depths of flaws (crushed layer) ΔD1 and ΔD2 caused to the semiconductor chip 1 in a dicing process are about 0.5 µm. Therefore, an influence of damages due to chipping can be reduced by processing the portion of the semiconductor chip 1 where the side surfaces 1SA to 1SD and the rear surface IRS cross into a shape having a curvature radius of at least 0.5 µm”).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include steps in the method of Topacio to round the corner surface as taught by Kurosawa to minimize the chipping of the dies during dicing. Thus, combination of Topacio and Kurosawa leads to a method comprising a side surface which is straight and rounded
Neither Topacio nor Kurosawa, however, teaches that the method comprises using a laser beam to shape the corner surface as being straight and rounded.
Park, on the other hand, teaches a method (Fig. 3; page 3, last three paragraphs) where the corners of a trench (trench 14, Fig. 3, third paragraph from the bottom) are rounded by a laser beam (page 3: the laser beam is scanned multiple times from different directions).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that Topacio also uses a laser grooving method (Fig. 11, [0038]: ”a laser source 276 may be used to cut a trench 277”) to form a trench (trench 277, Fig. 11), where the edges of the trench forms the corner surface (Fig. 11 and Illustrative Fig. 1) of Topacio. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to modify the method of Topacio according to the teachings of Park to use a laser beam for both forming the trench and shaping the corner surfaces as being straight and rounded, which would provide advantages over alternative methods (chemical or mechanical) for shaping the corners because no extra equipment would be required, and potential interference of alternative methods with device processing can be avoided.
Thus, the combination of Topacio, Kurosawa, and Park meets all the limitations of claim 22.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Topacio (US 2017/0301638 A1) as applied to claims 21 and 25 above, and further in view of Mohammed (US 2011/0155435 A1).
Regarding claim 24, while Topacio teaches the method of claim 21,
Topacio does not teach that the corner surface has a roughness smaller than about 1.5 µm.
Mohamed, on the other hand, teaches a method for dicing wafers (Figs. 11A-B, [0022]) using a picosecond laser wherein a surface roughness of 0.2 µm could be obtained ([0022]).
Mohammed further discloses that pulse duration is a strong factor to control surface roughness, and much smoother surface may be achieved with femto-second lasers. ([0022]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use a picosecond or femtosecond laser for laser grooving process to obtain a smooth corner surface that is acceptable for dicing (Mohamed, [0022] and claim 6). Thus, the combination of Topacio and Mohamed meets the limitation that the corner surface has a roughness smaller than about 1.5 µm.
Allowable Subject Matter
Rejected claims 26-28, which depend on rejected claim 21, would be allowable if the 35 U.S.C. 112 rejections are overcome, and if they are rewritten in independent form including all of the limitations of the base claim (claim 21) and any intervening claims.
Regarding Claim 26, disclosing that “an outer portion of the bottom surface extends laterally beyond the second edge, and the outer portion of the bottom surface is tilted with portions farther away from the second edge being lower than respective portions of the bottom surface closer to the second edge”, would be allowable if this limitation is incorporated in a claim including the limitations of claim 21 and if the 35 U.S.C. 112 rejection is overcome. Regarding the closest prior art, Topacio teaches all the limitations of claims 21, but fails to teach the limitation above, as in Topacio’s method, the bottom portion can be flat or tilted or curved in opposite direction than claimed. There has been no motivation or prior art identified that can modify the method of Topacio to render the invention of claim 26 obvious.
Claims 27 and 28 depend on claim 26, and therefore would be also allowable if claim 26 becomes allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi (US 2020/0312715 A1) teaches a method (Figs. 5-7) for forming a second trench by a laser grooving process in a wider first trench for dicing a semiconductor wafer, which is relevant to all claims.
Choi (US 2013/0161824 A1) teaches shaping the surface of a dielectric layer by using different numbers of pulses at different locations, which is relevant to all claims 4-7.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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