DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group I, claims 1-10 in the reply filed on July 20, 2026, is acknowledged.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 20, 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
Method for forming non-line-of-sight junctions by epitaxially depositing doped first and second junction layers using a reduced thermal budget
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description:
In ¶[0029] the specification refers to a “substrate 302” in Fig. 2. However, the substrate is identified as (202) in Fig. 2. It is assumed ¶[0029] should be corrected to refer to a “substrate 202.”
In ¶[0043] reference is made to a substrate (405) which does not appear to be shown in Figs. 4A-B.
In ¶[0067] reference is made to a capping layer (305) which does not appear to be shown in Figs. 3-4.
In ¶[0074] the specification refers to a post-anneal operation (425) which is not shown in Fig. 3. It is assumed applicants intended to refer to the post-anneal (330).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
The term “low thermal budget” in l. 3 of claim 1 is a relative term which renders the claim indefinite. The term “low” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Since neither the specification nor the claims as filed clearly define how low the thermal budget must be in order to be considered as a “low thermal budget feature,” its recitation in claim 1 is therefore considered to be indefinite. Dependent claims 2-10 are similarly rejected due to their direct or indirect dependence on claim 1.
The use of the term “about” in claims 1-3 and 8 is a relative term which renders the claims indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The use of the term “about" is permissible since it permits some tolerance, and therefore encompasses values on either side of the claimed value or number. In re Pappas, 214 F. 2d 172, 176-177, 102 USPQ 298, 301 (CCPA 1954). However, applicants have not clearly exemplified the amounts above and below the claimed values which may be encompassed by the use of the word “about.”
Claim Rejections - 35 USC §§ 102 and 103
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by or, alternatively, under 35 U.S.C. 103 as being unpatentable over U.S. Patent Appl. Publ. No. 2022/0059703 to Shahaji More (hereinafter “More”).
Regarding claim 1, More teaches a semiconductor processing method (see the Abstract, Figs. 1-22, and entire reference which teach a method of processing a semiconductor) comprising:
providing a semiconductor structure with one or more undoped non-line-of-sight target regions on a substrate within a semiconductor processing chamber, wherein one or more low thermal budget features are formed on the semiconductor structure (see Figs. 19A-D and ¶¶[0081]-[0095] which teach providing a semiconductor FIN structure (11) with a source/drain space (21) on a substrate which is necessarily placed within a processing chamber in order to perform the desired bake and epitaxial deposition operations; moreover, the FIN structure (11) includes nanostructures (25) formed thereupon which, as disclosed in at least ¶[0055], are formed using a low temperature such as 60 to 90°C to etch the source/drain space (21));
epitaxially depositing a first junction layer having a first dopant concentration of less than 1 x 1020 dopant atoms per cm3 over the substrate (see Fig. 19B and ¶[0086] which teach depositing a first epitaxial layer (50-1) with a B dopant concentration of 5×1019 atoms/cm3);
epitaxially depositing a second junction layer having a second dopant concentration of greater than 1 x 1019 dopant atoms per cm3 over the first junction layer (see Fig. 19C and ¶[0091] which teach the deposition of a second epitaxial layer (50-2) with a B dopant concentration of 5×1019 atoms/cm3);
wherein a temperature within the semiconductor processing chamber is maintained at less than or about 800 °C (see ¶[0089] and ¶[0092] which teach that the process temperature for forming the first (50-1) and second (50-2) epitaxial layers ranges from 550 to 750 °C which necessarily means that the temperature within the processing chamber is also less than 800 °C; alternatively, a PHOSITA prior to the effective filing date of the invention would be motivated to maintain the temperature within the processing chamber at less than 800 °C in order to ensure that the substrate temperature stays within the desired range of 550 to 750 °C).
Regarding claim 2, More teaches that the temperature within the semiconductor processing chamber is maintained at less than or about 750 °C (see ¶[0089] and ¶[0092] which teach that the process temperature for forming the first (50-1) and second (50-2) epitaxial layers ranges from 550 to 750 °C which necessarily means that the temperature within the processing chamber is also less than 800 °C; alternatively, a PHOSITA prior to the effective filing date of the invention would be motivated to maintain the temperature within the processing chamber at less than 800 °C in order to ensure that the substrate temperature stays within the desired range of 550 to 750 °C).
Regarding claim 3, More teaches subjecting the one or more undoped non-line-of-sight target regions to a hydrogen bake prior to epitaxially depositing the first junction layer, wherein the hydrogen bake is conducted at a temperature of less than or about 750 °C (see ¶[0083] which teaches that a pre-clean operation is performed at a temperature of 500-600 °C in a NHpre- plasma before depositing the first (50-1) and second (50-2) epitaxial layers which necessarily involves the use of H atoms and may be broadly considered as a hydrogen bake; see also ¶[0089] and ¶[0091] which teach performing a baking/annealing operation before epitaxial deposition)
Regarding claim 4, More teaches that the one or more undoped non-line-of-sight target regions is disposed in a recess located within the semiconductor structure (see Figs. 19A-D and ¶¶[0081]-[0095] which teach that the FIN structure (11) includes a recess in the form of the source/drain space (21) where the first (50-1) and second (50-2) epitaxial layers are formed therein).
Regarding claim 5, More teaches that the one or more undoped non-line-of-sight target regions is disposed within a feature having a width of 10 nm or less (see ¶[0032] and ¶[0042] which teach that the width and/or thickness of the nanostructures (25) and (20) may be as small as 5 nm; see also Fig. 8 and ¶[0057] which teach forming inner spacers (35) with a recessed amount of about 0.2 to 3 nm).
Regarding claim 6, More teaches that the semiconductor structure is maintained in an oxygen free atmosphere during the pre-clean operation, during epitaxially depositing the first junction layer, during epitaxially depositing the second junction layer, or a combination thereof (see ¶¶[0081]-[0095] which teach that the pre-clean and epitaxial growth steps are performed using gaseous precursors which do not include oxygen and, hence are performed in an oxygen-free atmosphere; see specifically ¶[0095] which teach that the process steps may be performed as an in-situ deposition process which avoids the potential for atmospheric contamination with oxygen).
Regarding claim 7, More teaches that the pre-clean operation is integrated into the semiconductor processing chamber (see ¶[0095] which teach that the process steps may be performed sequentially as an in-situ deposition process which necessarily avoids the potential for atmospheric contamination with oxygen and, consequently, this means that the pre-clean step is integrated with the processing chamber; alternatively, a PHOSITA prior to the effective filing date of the invention would be motivated to utilize the same processing chamber for both the pre-clean and epitaxial deposition processes as part of an operation that is performed entirely in-situ in order to avoid the propensity for contamination from the ambient).
Claim Rejections - 35 USC § 103
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over More in view of U.S. Patent Appl. Publ. No. 2020/0135894 to Chan, et al. (“Chan”).
Regarding claim 8, More teaches annealing the semiconductor structure after epitaxially depositing the second junction layer, wherein the annealing is conducted at a temperature of less than or about 1100 °C. However, in Figs. 1A-B & 10A and ¶¶[0013]-[0044] as well as elsewhere throughout the entire reference Chan teaches an analogous method of forming a finFET which includes, inter alia, the deposition of a first layer (260) into a recess in step (108) and then the deposition of a second layer (236) in step (114). The deposition of the first (260) and second (236) layer is followed by an annealing process in steps (112) and (126). This is specifically disclosed in at least ¶[0031] and ¶[0036] which teach that the annealing step is performed at a temperature in the range of 900 to 1,050 °C for 1 to 2 seconds in order to activate the dopant species and/or to repair the crystalline structure. Thus, a PHOSITA prior to the effective filing date of the invention would be motivated to perform an annealing step on the second epitaxial layer (50-2) in the method of More at a temperature in the overlapping range of 900 to 1,050 °C in order to activate the dopant species and produce a higher quality crystalline layer.
Regarding claim 9, More teaches forming a dopant gradient extending from an exterior surface of the second junction layer to the substrate (see at least ¶[0091] which teaches that the average B concentration of the second epitaxial layer (50-2) may be higher than the largest B concentration of the first epitaxial layer (50-1) which necessarily produces a dopant gradient from the surface of the second layer (50-2) to the substrate), but does not teach that the annealing is conducted for a period of time and/or a temperature to form a linear dopant gradient or a logarithmic dopant gradient. However, as noted supra with respect to the rejection of claim 8, in Figs. 1A-B & 10A and ¶¶[0013]-[0044] as well as elsewhere throughout the entire reference Chan teaches an analogous method of forming a finFET which includes, inter alia, the deposition of a first layer (260) into a recess in step (108) and then the deposition of a second layer (236) in step (114). The deposition of the first (260) and second (236) layer is followed by an annealing process in steps (112) and (126). This is specifically disclosed in at least ¶[0031] and ¶[0036] which teach that the annealing step is performed at a temperature in the range of 900 to 1,050 °C for 1 to 2 seconds in order to activate the dopant species and/or to repair the crystalline structure. Thus, a PHOSITA prior to the effective filing date of the invention would be motivated to perform an annealing step on the second epitaxial layer (50-2) in the method of More at in order to activate the dopant species and produce a higher quality crystalline layer. In this case, since the combination of More and Chan perform each and every step of the claimed process, the annealing method of Chan would necessarily produce either a linear or logarithmic dopant gradient as claimed. It is axiomatic that one who performs the steps of the known process must necessarily produce all of its advantages. Mere recitation of a newly discovered function or property, that is inherently possessed by things in the prior art does not cause a claim drawn to these things to distinguish over the prior art. Therefore, a linear or logarithmic dopant gradient, if not clearly envisaged, would be reasonably expected by the skilled artisan. See Leinoff v. Louis Milona & Sons, Inc. 220 USPQ 845 (CAFC 1984).
Claims 10 are rejected under 35 U.S.C. 103 as being unpatentable over More in view of Chan and further in view of U.S. Patent No. 11,164,872 to Pulugurtha, et al. (“Pulugurtha”).
Regarding claim 10, More does not teach that the one or more low thermal budget features include a bitline contact. However, in Fig. 1 and col. 2, l. 32 to col. 4, l. 10 as well as elsewhere throughout the entire reference Pulugurtha teaches an analogous method of producing underbody contacts for vertical three-dimensional (3D) memory using a digit line and horizontal access devices in an array of vertically stacked memory cells. In Fig. 1 and col. 3, ll. 7-21 Pulugurtha specifically teaches an embodiment of a 3D memory device which includes a plurality of sub cell arrays, 101-1 through 101-N which are arranged along a second direction (D2). Each of the sub-cell arrays 101-1 through 101-N include a plurality of access lines 103-1 through 103-Q extending in direction (D3) and a plurality of digit lines 107-1 through 107-Q which are known as bitlines extending in direction (D1). Each individual memory cell (110) is capable of being uniquely addressed through a combination of an access line and a bitline. Thus, a PHOSITA prior to the effective filing date of the invention would be motivated to include bitline contacts to the FIN structure (11) formed in the method of More and Chan in order to permit each memory cell to be uniquely addressed during operation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH A BRATLAND JR whose telephone number is (571)270-1604. The examiner can normally be reached Monday- Friday, 7:30 am to 4:30 pm EST.
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/KENNETH A BRATLAND JR/Primary Examiner, Art Unit 1714
