DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
1. Claims 2-21 are present for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
2. Claims 2-4, 6-11, 13-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 6-11, 14-16 & 18 of U.S. Patent No. 11,990,177 (same assignee/inventor). Although the claims at issue are not identical, they are not patentably distinct from each other because the following claim comparisons:
Claims 2 & 9 (from this application), each recites a logic IC base die (including a primary interface) and a multiple memory dies (including multiple/independent interfaces) stacked on the base die, and each such individual memory interface is also configured to couple to a corresponding one of the multiple independent secondary interfaces of the logic/base die in a dedicated manner, which are all obviously seen in claims 1 & 9, respectively (from patent above).
Claims 3 & 10 (from application) recite the usage for the “multiple serial signal I/O circuits”, which also obviously read on the “multiple serial signal paths” of the patent’s claims 2 & 10, respectively (from patent) because it is well-known that any signal paths should have both signal input and output circuits.
Claims 4 & 11 (application) obviously recite similar usage of a DRAM type for the multiple memory dies, which also seen from patent claims 3 & 11 (patent), respectively.
Claims 6-8 & 13-15 (application) recite identical language with claims 6-8 & 14-15, respectively (patent).
Claim 16 (application) recites a method for communicating between a memory controller and multiple memory dies through these memory stacks using first & secondary memory interfaces, etc., which are also obviously seen with similar language from claim 16 (patent).
Claim 17 (application) recite the usage for the “multiple serial signal I/O circuits”, which also obviously read on the “multiple serial signal paths” of the patent’s claims 2 & 10, respectively (from patent) because it is well-known that any signal paths should have both signal input and output circuits.
Claims 18-21 (application) recite identical language with claims 18 & 6-8, respectively (patent).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(e) the invention was described in a patent granted on an application for patent by another filed in the United States before the invention thereof by the applicant for patent, or on an international application by another who has fulfilled the requirements of paragraphs (1), (2), and (4) of section 371(c) of this title before the invention thereof by the applicant for patent.
The changes made to 35 U.S.C. 102(e) by the American Inventors Protection Act of 1999 (AIPA) and the Intellectual Property and High Technology Technical Amendments Act of 2002 do not apply when the reference is a U.S. patent resulting directly or indirectly from an international application filed before November 29, 2000. Therefore, the prior art date of the reference is determined under 35 U.S.C. 102(e) prior to the amendment by the AIPA (pre-AIPA 35 U.S.C. 102(e)).
3. Claims 2-4, 9-11, 16-18 are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Rajan et al (US 9,171,585).
Claims 2, 4, 9, 11, 16, 18, Rajan (Fig. 2) clearly shows an integrated circuit (IC package 201) comprising at least a base/control die (or buffer die/chip 202) and a multiple/stacked memory dies (or DRAM chips 206A to 206D) mounted above its surface and on substrate of the whole IC package. Each individual memory die (i.e., 206A-206D) also has its own interface coupled to internal I/O bus (208) for coupling various signals (i.e., control clock, address & data) from each chip to/from the primary interface of a buffer/control chip, thus these individual chip has its own/independent interface coupling to/from the primary interface of buffer chip 202.
[AltContent: arrow][AltContent: textbox (A base/logic die = buffer chip 202, and multiple memory dies = stacked DRAM chips 206A-206D
Local/memory independent interfaces = 4 signal/arrows go into 4 independent/internal circuits of each DRAM chip 206A-206D, and
Primary interface = 5 signal/arrows go down into the internal circuit inside the buffer chip 202, see Fig. 200A further below.)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Individual interfaces)]
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Additionally, Fig. 200A below shows usage of multiple independent/secondary interfaces exist in the logic/base die for handling multiple/independent date bursts, which are to be read or write from each independent memory dies as claimed.
[AltContent: textbox (Multiple independent/secondary interfaces for
communication with data bursts from
plural DRAM chips)][AltContent: textbox (Primary data interface = Data path logic 20081 + System data signal interface circuit 20074 inside base die
Multiple secondary interfaces = multiple memory data interfaces A to X (20078) inside the logic die.
Each of these multiple secondary interface (inside logic/base die) will communicating each different data burst (i.e., 20010 to 20030) from/to a respective memory die interface to/from the primary interface 20081, or vice versa, in a dedicated R/W manner, using the DRAM signaling protocol, and via a time-interleaving format with synchronizing clocks, see also timing diagrams of Figs. 200B-200D for more details.)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Data bursts to/from multiple
memory interfaces of multiple dies go
through different signal paths A to X)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Primary data interface of logic die)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox ()]
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Claims 3, 10 & 17, Fig. 58B shows the serial interface circuit with serial links (5841/5846) sit between the controller (of logic die) and the multiple memory DRAM dies (DRAMs 5840-5852) for transferring serialize signals between them as claimed. Additionally, col. 58 (lines 8-25) stated that “… the interface circuits 2502 may be configured or connected in parallel, serially, or in various combinations thereof. The multiple interface circuits 2502 may use direct connections to each other, indirect connections to each other, or even a combination thereof”, which also obvious to a skilled person in this art that a “serial DRAM signal protocol” has been suggested as well.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 5 & 12 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Rajan et al (US 9,171,585) in view of Loh et al (US 2013/0159812).
Claims 5 & 12 add the limitations of employing two different fabrication processes forming two different dies (i.e., memory die and logic die). However, such knowledge is considered as conventional techniques in this art in view of other prior art teachings.
For example, prior art of Loh et al (Fig. 1A-1B) below shows two circuit configurations, which includes two different types of chips with two separate and independent I/O interfaces, i.e., a stacked memory die/chip and a logic/control die/chip formed onto same substrate surface, and each type of chip is formed by a different process as claimed. See excerpts below:
[0012] Memory architecture of a memory device is provided that includes one or more memory chips (e.g., storage chips or layers) and a separate logic chip (e.g., logic specific chip or layer) on a single die (e.g., die-split memory, such as a stacked memory or a side-split memory). By providing one or more memory chips and a separate logic chip, the memory architecture can be used to perform different operations from a memory device with a single die that includes storage and logic on the chip.
[0013] In one implementation, a logic operation can be run by the separate logic chip to take advantage of logic located on the separate logic chip in the memory architecture. For example, the logic, of the logic chip of the memory architecture, can perform a read-modify-write operation that can occur within the memory architecture without transferring data to or from a processor outside of the memory architecture.
[0014] In another implementation, a logic chip can be manufactured using a different process from storage chips or memory chips.
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Thus, it would have been obvious to a skilled person in this art, at the time of invention, to smartly employ different manufacturing processes forming these two types of chips (as suggested by Loh patent) onto the similar memory architecture of Rajan device, without hindrance or hindsight, so as to have a better efficient die layout and also to be able to reduce manufacturing costs as well.
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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/VIET Q NGUYEN/ Primary Examiner, Art Unit 2827