Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 8/31/2026 is acknowledged.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10-12, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Io (US 20090166708 A1).
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CLAIM 1. Io teaches a transistor structure, comprising:
a substrate 1;
an isolation structure 5/20 located in the substrate and defining an active region in the substrate, wherein the isolation structure protrudes from a top surface of the substrate to form a recess above the active region;
a gate FG located on the substrate and comprising:
a first portion FG-L located in the recess; and
a second portion FG-U located on the first portion and located directly above a portion of the isolation structure; and
a gate dielectric layer 10 located between the first portion and the substrate, between the first portion and the isolation structure, and between the second portion and the isolation structure (Io Fig. 2B).
CLAIM 1. Io teaches the transistor structure according to claim 1, wherein the width of the first portion is smaller than a width of the second portion (Io Fig. 2B).
CLAIM 3. Io teaches the transistor structure according to claim 1, wherein a width of the first portion is smaller than a width of the active region (Io Fig. 2B).
CLAIM 4. Io teaches the transistor structure according to claim 1, wherein a cross-sectional shape of the gate comprises a T-shape (Io Fig. 2B).
CLAIM 5. Io teaches the transistor structure according to claim 1, wherein a cross-sectional shape of a portion of the gate dielectric layer located between the first portion and the substrate and between the first portion and the isolation structure comprises a U-shape (Io Fig. 2B).
CLAIM 6. Io teaches the transistor structure according to claim 1, wherein the isolation structure 5/20 has a first upper surface and a second upper surface, the first upper surface is located between the second upper surface and the gate, and the first upper surface is higher than the second upper surface (Io Fig. 2B – Dielectric layer 12 in combination with Dielectric material 5 create a analogous notched structure as described.).
CLAIM 7. Io teaches the transistor structure according to claim 1, wherein the isolation structure 5/20 has a notch, and the notch is located on one side of the isolation structure away from the active region (Io Fig. 2B – Dielectric layer 12 in combination with Dielectric material 5 create a analogous notched structure as described.).
CLAIM 10. Io teaches the transistor structure according to claim 1, further comprising: a spacer located on a sidewall of the gate dielectric layer (Io Fig. 2B).
CLAIM Io teaches the transistor structure according to claim 10, wherein the spacer 20 is further located on a sidewall of the second portion (Io Fig. 2B- portion of dieletric layer 20 located on sidewall of gate structure.).
CLAIM 12. Io teaches the transistor structure according to claim 10, wherein the spacer is further located on a sidewall of the isolation structure and an upper surface of the isolation structure (Io Fig. 2B – Dielectric portion 20 is located on both a sidewall and an upper surface.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Io (US 20090166708 A1) in view of Takahashi et al. (US 20060086971 A1).
CLAIM 8. Io teaches the transistor structure according to claim 1, however is silent upon the capability of wherein the gate dielectric layer comprises: a first dielectric layer located on the substrate in the active region; a second dielectric layer located on the first dielectric layer; and a third dielectric layer located on the second dielectric layer, a sidewall of the isolation structure, and an upper surface of the isolation structure.
However, Takahasi discloses an analogous semiconductor transistor device structure incorporating a multi-layer gate dielectric layer. Specifically, as shown in Figure 1, Takahasi discloses a tri-layer oxide-nitride-oxide (ONO) gate dielectric 56 that is located under the T shaped gate profile having a lower portion recessed and an upper portion [including a sidewall) which overlaps the notched shallow trench isolation (STI) structure 52 defining the active region of the transistor, and explicitly conforms to the topography such that it sits on the substrate, the sidewall of the isolation structure, and an upper surface of the isolation structure.
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It would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention to modify the device of Io by replacing Io's single-layer gate dielectric with the tri-layer ONO gate dielectric structure taught by Takahasi.
A PHOSITA would be motivated to implement this modification because tri-layer gate dielectrics (such as ONO stacks) were well-known, staple building blocks in the semiconductor art at the time of the invention to improve charge retention, prevent leakage current, and optimize the dielectric constant in transistor devices. Substituting one known dielectric layer for a known multi-layer stack to achieve these predictable electrical enhancements represents nothing more than the predictable use of prior art elements according to their established functions (see KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007); MPEP § 2143, Exemplary Rationales A and E).
Furthermore, regarding the structural layout and placement of the third layer over the sidewall and top surface of the isolation structure, this configuration is the predictable result of standard, conformal deposition techniques (such as Chemical Vapor Deposition or Atomic Layer Deposition) routinely used by a PHOSITA when depositing material layers over topography defined by an active region and an STI edge.
Per MPEP § 2141.03, the prior art must be considered from the perspective of the PHOSITA, who is presumed to bring the common knowledge and technological expectations of the core art to the table. Because ONO dielectric configurations on active/STI boundaries were commonplace in the art (as demonstrated by Takahasi), rearranging or executing these layers in the recited structural sequence provides no unexpected results and is within the routine skill of the practitioner.
CLAIM 9. Io in view of Takahasi teaches the transistor structure according to claim 8, wherein the first dielectric layer, the second dielectric layer, and a portion of the third dielectric layer are located in the recess (Io as modified by Takahasi Fig. 1- Furthermore, regarding the structural layout and placement of the third layer over the sidewall and top surface of the isolation structure, this configuration is the predictable result of standard, conformal deposition techniques (such as Chemical Vapor Deposition or Atomic Layer Deposition) routinely used by a PHOSITA when depositing material layers over topography defined by an active region and an STI edge.)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
9/29/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898
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