Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 1/2/2025 and 10/16/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 24 is objected to because of the following informalities: the language in lines 3-4 “wherein forming of the trench comprises implements the patterned hard mas as an etch mask” is grammatically incorrect and unclear. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuo (US 20240047552 A1).
Regarding claim 21, Kuo discloses, in FIG. 8B, a method comprising: forming a trench extending into a substrate, 152 (which is a substrate as layers and components are later formed thereon), performing an etching process to trim a first portion of the substrate exposed by a top portion of the trench without substantially etching a second portion of the substrate exposed by a bottom portion of the trench (FIG. 8C); after the performing of the etching process, forming a capacitor in and over the trench ([0054] “The final DTC structure 64 is further illustrated in FIG. 8G . . .” the examiner notes that [0034] introduces “DTC” to stand for “Deep Trench Capacitor”; and forming a dielectric layer 204 over the capacitor and in and over the trench (FIG. 8E).
Regarding claim 22, Kuo further discloses, in FIG. 8B, that the width of the trench is non-uniform. The examiner also notes that FIG. 8E also shows this.
Regarding claim 23, Kuo further discloses, in FIG. 8C, that after the performing the etching process, the first portion of the substrate has rounded corners.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 20240047552 A1) in view of Lim (US 6228727 B1).
Regarding claim 1, Kuo teaches, in FIG. 8A, a method comprising forming a patterned hard mask 192 ([0045]: “In alternative embodiments, the etch mask 192 is a hard etch mask . . .”) over a substrate 152, the patterned hard mask exposing a first portion of the semiconductor substrate and covering a second portion of the semiconductor substrate adjacent to the first portion, wherein the second portion comprises an upper part in direct contact with the patterned hard mask and a lower part; performing a first etching process (FIG. 8A to FIG. 8B) to recess the first portion and the lower part of the second portion to form a trench 194 ([0048] “In some embodiments, the deep trenches 150 are formed in the substrate 142 including silicon”); performing a second etching process (FIG. 8b to FIG. 8C) to trim corners of the upper part of the second portion, and removing the patterned hard mask (FIG. 8A to FIG. 8B); and forming a capacitor in and over the trench ([0054] “The final DTC structure 64 is further illustrated in FIG. 8G . . .” the examiner notes that [0034] introduces “DTC” to stand for “Deep Trench Capacitor”). The examiner notes that the “dielectric layer” 152 is a substrate because there are layers and components thereon; further, [0048] states that “In some embodiments, the deep trenches 150 are formed in the substrate 142 including silicon . . .” meaning that Kuo teaches the previous steps etching into a semiconductor substrate.
Kuo does not teach a selective removal of the patterned hard mask after the performing of the second etching process.
Lim teaches, in FIGs. 7-17, a method comprising: forming a patterned hard mask (paragraph 4: “the silicon nitride layer 48 and the pad oxide layer 44 are patterned to form a hard mask”) over a semiconductor substrate (40), the patterned hard mask exposing a first portion of the semiconductor substrate and covering a second portion of the semiconductor substrate adjacent to the first portion, wherein the second portion comprises an upper part in direct contact with the patterned hard mask and a lower part; performing a first etching process to recess the first to form a trench (FIG. 10); performing a second etching process to trim corners of the trench (FIG. 12), and, after the performing of the second etching process, selectively removing the patterned hard mask (FIG. 17).
It would have been obvious to one having ordinary skill in the art to modify the device taught by Kuo such that the hard mask is removed after the second etching step, as taught by Lim. One having ordinary skill in the art is motivated to do so because, for example, removing the hard mask allows for other components to take its place, or for the elimination of the problem of oxide recession (Lim bottom of paragraph 16). See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 2, Kuo further teaches, in FIG. 8D, that after the performing the second etching process, the corners of the upper part of the second portion are rounded corners.
Regarding claim 3, Lim further teaches, in paragraph 8: “Referring now to FIG. 10 the first etching step] . . . A conventional dry etching process is used to create the trenches. The dry etching chemistry comprises Ar, O.sub.2, CF.sub.4, and CHF.sub.3.” Paragraph 11 states: “The rounding of the trench corners depicted in FIG. 12 can also be accomplished through use of a hydrogen anneal.”
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the method taught by Kuo such that the etchant of the first etching process is different the etchant of the second process, as taught by Lim. One having ordinary skill in the art is motivated to do so because, for example, the first dry etching step is “conventional” (Lim, paragraph 8), meaning the results are predictable and/or the cost thereof is low, and, for the second etching step, “In a hydrogen anneal step, etch induced stresses in the semiconductor substrate 40 are relieved.”
Regarding claim 4, Kuo further teaches, in [0046]: “Referring to FIG. 8B [the first etch step] . . . In the disclosed embodiment, the etching process includes a dry etching process using an etchant containing fluorine, chlorine or a combination thereof, such as silicon tetrafluoride (SiF.sub.4)”
Regarding claim 5, Lim further teaches, in paragraph 8: “Referring now to FIG. 10 [the first etch step] . . . A conventional dry etching process is used to create the trenches. The dry etching chemistry comprises Ar, O.sub.2, CF.sub.4, and CHF.sub.3.”
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the method taught by Kuo such that the second etching process comprises implementing argon. One having ordinary skill in the art is motivated to do so because, for example, argon is chemically inert, ensuring that no chemical damage is done to the exposed substrate.
Regarding claim 9, Kuo further teaches, in FIG. 8D (after all hard masks are removed) and [0048] “ . . . dielectric liner 202 is an oxide layer . . . In some embodiments, the deep trenches 150 are formed in the substrate 142 including silicon, the formation of the dielectric liner 202 includes performing a thermal oxidation process in a furnace in an environment containing oxygen.”
Regarding claim 10, Kuo further teaches, in [0048]: “In some embodiments, the dielectric liner 202 has a thickness ranging between 10 angstrom and 500 angstrom . . .” the examiner notes that this teaches a non-uniform thickness (“between 10 angstrom and 500 angstrom”) of the oxide layer 202.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 20240047552 A1) in view of Lim (US 6228727 B1) in further view of Mui (US 6235643 B1).
Regarding claim 6, as explained above, Kuo and Lim teach the limitations of claim 1. They do not explicitly teach that a process pressure of the second etching process is lower than 20 millitorr.
Mui teaches, in Mui teaches, in FIG. 4B, an etching step into substrate 402 using a patterned “photoresist” layer (see paragraph 32) acting as a hard mask for a “break through step” which etches the substrate in order to create rounded structure 412 on the substrate. Table Two, Table Three, Table Four, and Table Five all show etching specifications including Run # 1, 2, 5, 7-14,16, and 26 which all have a process pressure of less than 20 millitorr.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the second etching process taught by Kuo such that a process pressure thereof is less than 20 millitorr, as taught by Mui. One having ordinary skill in the art is motivated to do so because, for example, all of these processes have well known silicon etch rates, meaning that the results are predictable and can be utilized with a high-yield; the examiner notes that it is obvious to try one of these pressures from a finite number of process parameters taught by Kuo. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 7, as explained above, Kuo teaches a silicon oxide hard mask and the rounding of corners of a silicon substrate in a second etching process.
Kuo does not explicitly teach that the performing of the second etching process further reduces a dimension of the patterned hard mask.
As explained above, Mui teaches an etching step for forming rounded corners in a silicon substrate and a nonzero etching selectivity between silicon and silicon oxide. Kuo further teaches, because “One of the plasma feed gas recipes which provides excellent results is a combination of CF.sub.4, HBr, and argon” (paragraph 15), and Table Two further shows that processes involving CF4, HBr, and Ar have a nonzero etch rate with Silicon Oxide.
It would have been obvious to one having ordinary skill in the art at the effective filing date to utilize one of the CF4, HBr, and Ar etching processes taught by Mui to perform the second etching step of Kui (in other words, such that the performing of the second etching process further reduces a dimension of the patterned hard mask). One having ordinary skill in the art is motivated to do so because, for example, this etching process “provides excellent results” as taught by Mui above.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 20240047552 A1) in view of Lim (US 6228727 B1) in further view of Brodsky (US 20140191366 A1).
Regarding claim 8, as explained above, Kuo and Lim teach the limitations of claim 8. They do not explicitly teach that after the performing of the second etching process, the upper part spans a first width, and a topmost surface of the upper part spans a second width less than the first width.
Brodsky teaches, in FIG. 4 (related art), a deep trench “enlarged with bottle process” which has a first portion not covered by a hard mask (see FIG. 1 and [0021]: “The combination of pad oxide 16 and pad nitride 18 can be etched selectively to each other and, when patterned (e.g. using a resist layer, not shown) that can be selectively exposed to energy which develops differential solubility to form a pattern), provide a hard mask for etching of the semiconductor layer 14, the insulator later 12 and the handling substrate 10”) in which the upper part spans a first width, and a topmost surface of the upper part spans a second width less than the first width.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the method taught by Kuo such that, after the performing of the second etching process, the upper part spans a first width, and a topmost surface of the upper part spans a second width less than the first width, as taught by Brodsky. One having ordinary skill in the art is motivated to do so in order to, for example “. . . further increase the area of the interior of the deep trenches . . .” ((Brodsky, [0022]), which increases the capacitance of a capacitor formed therein.
Claim(s) 11-16 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 20240047552 A1) view of Mui (US 6235643 B1).
Regarding claim 11, Kuo teaches, in FIG. 8A, a method, comprising: forming a patterned mask 192 over a substrate 152 (the examiner notes that 152 has components and layers formed on it, and therefore it is a substrate); performing a first etching process using the patterned mask as an etch mask to etch the substrate to form a trench (FIG. 8B), wherein a width of the trench is not uniform from bottom to top; performing a second etching process (FIG. 8C), wherein the performing of the second etching process trims a portion of the substrate under the patterned mask; selectively removing the patterned mask; and forming a capacitor in and over the trench ([0054] “The final DTC structure 64 is further illustrated in FIG. 8G . . .” the examiner notes that [0034] introduces “DTC” to stand for “Deep Trench Capacitor”).
Kuo does not explicitly teach that performing the second etching process reduces a width of the patterned mask.
Mui teaches, in FIG. 4B, an etching step into substrate 402 using a patterned “photoresist” layer (see paragraph 32) acting as a hard mask for a “break through step” which etches the substrate in order to create rounded structure 412 on the substrate: paragraph 38 mentions adding a nonreactive gas to the plasma etchant for this corner-rounding step, to increase the selectivity of etching between the silicon oxide which will form on the substrate and the photoresist layer (see paragraph 36), meaning that the photoresist layer is partially etched by this step, and thus that the width of the photoresist (which is a mask) is reduced in the corner rounding step. The examiner further notes that “Table Two” further details the reduction of photoresist during this step (see the “photoresist etch” and “selectivity” rows.
It would have been obvious to one having ordinary skill in the art at the effective filing date that to utilize a plasma etching step using any of the etchants detailed by Mui (see Table Two) in the second etching step of Kuo, such that the width of the mask is reduced. One having ordinary skill in the art is motivated to do so because, for example, the etching rates of such etchants are well known (Mui, Table Two), allowing for the precise rounding of corners, increasing yield. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 12, as explained above, Mui teaches, in FIG. 4B and paragraph 38, the use of a plasma etchant in a corner-rounding step of a substrate.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the method taught by Kuo such that the second etching step comprises a plasma etch, as taught by Mui. One having ordinary skill in the art is motivated to do so because, for example, Othe etching rates of such etchants are well known (Mui, Table Two), allowing for the precise rounding of corners, increasing yield. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 13, Kuo further teaches, in [0046]: “In the disclosed embodiment, the [first] etching process includes a dry etching process using an etchant containing fluorine . . .” and in [0047]: “The second etching process is similar to the first etching process in FIG. 8B in terms of etchant . . .”
Kuo does not teach that the second etching step implements argon.
Mui teaches, in paragraph 36, of a corner-rounding step: “the principal etchant of the break-through etch plasma is generated from a feed gas containing fluorine which may be, by way of example and not by way of limitation, selected from the group consisting of CF.sub.4, CHF.sub.3, CH.sub.2 F.sub.2, CH.sub.3 F, and combinations thereof. The principal etchant is preferably selected from the group consisting of CF.sub.4, CHF.sub.3, and combinations thereof; and CF.sub.4 has been shown to work very well . . . The plasma feed gas preferably further includes a nonreactive, diluent gas selected from the group consisting of argon, helium, xenon, krypton, and combinations thereof. The nonreactive, diluent gas is most preferably argon.” The examiner notes that in plasma etching, the aforementioned compounds are implemented as gasses.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the second etching step taught by Kuo such that the performing of the second etching process comprises implementing a combination of argon and a fluorine-containing gas, as taught by Mui. One having ordinary skill in the art is motivated to do so because, for example, “the fluorine and the bombardment atoms (typically argon) provide for removal of native oxide layers” (Mui, paragraph 15) and because “One of the plasma feed gas recipes which provides excellent results is a combination of CF.sub.4, HBr, and argon” (Mui, paragraph 15).
Regarding claim 14, Mui teaches, in Table Two, a series of etchants (gas glows, power sources, pressures, etc.), along with silicon (substrate) etching rates (note that Kuo teaches etching into a silicon substrate, see above) and photoresist (mask) etching rates. The examiner notes that the first etching step taught by Kuo would preferably have a higher etching rate of silicon.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify select an etchant for the first etching step taught by Kuo such that the silicon etching rate thereof is high (such as run numbers 1 and 2 in Table Two taught by Mui, comprising SF6 and HBr) and a CF4 and Ar containing etchant for the corner rounding (second) step (such as run # 7 taught by Mui in Table Two). One having ordinary skill in the art is motivated to use a high silicon etch rate etchant for the step because, for example, the first etching step involves the formation of a trench, requiring more silicon removal, and is motivated to use CF4 and Ar containing etchant for the corner rounding (second) step for the reasons taught above; the examiner notes that, in Mui Table Two, these etchants for the first step (runs number 1 and 2) etches the patterned mask at a first rate, and the etchants for the second step (run number 7) etches the substrate at a second rate higher than the first rate.
The examiner further notes that the applicant has not disclosed that the second etching process etching the patterned mask at a second rate higher than the first rate provides an advantage, is used for a particular purpose, or solves a stated problem other than the well-known and unsurprising function of etching into the substrate.
Therefore, it would have further been obvious to one having ordinary skill in the art to modify the method taught by Kuo such that the first etching process etches the patterned mask at a first rate, the second etching process etches the patterned mask at a second rate higher than the first rate, because the etching rates of the mask by etchants are not relevant to the end product produced by the method (as the mask is later removed), so long as enough mask remains for it to continue functioning as a mask in later steps. Therefore, a combination of etchants for use in the first and second etching processes that meet this specification would have been known to one of ordinary skill in the art to be one of several design variations for creating a trench with rounded corners because the final structure would be equivalent and therefore the methods would perform equally well.
Regarding claim 15, Mui further teaches, in Table Two, that the rate of etching a silicon substrate (Si Etch Rate) is larger than the mask etch rate (Photoresist Etch Rate) in the preferred SF4 and Ar containing etch steps (see Run # 6 and 7).
It would have been obvious to one having ordinary skill in the art at the effective filing date to select an etchant for the second etching processes taught by Kuo such that the etchant etches the substrate at a higher rate than the mask (or in other words, such that the second etching process etches the substrate at a third rate higher than the second rate) as taught by Mui. One having ordinary skill in the art is motivated to do so because, for example, this enables a deeper trench to be formed (as the trench can be made deeper before the full mask is etched away), allowing for a higher-capacitance capacitor to be filled in the trench.
Regarding claim 16, Mui further teaches, FIG. 5C, a mask comprising “patterned silicon nitride hard mask” 506 and “built-up structure” 508. FIG. 5C shows a step of etching a trench (depth A) in a substrate 502 with rounded upper corners 512 and FIG. 5D shows the removal of the mask layer 108 and an additional etching step further etching the portion of the substrate under the mask to depth B.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the method taught by Kui such that the patterned mask comprises a first mask layer over a second mask layer, the method further comprising: performing a third etching process to further trim the portion of the substrate under the patterned mask, wherein the selectively removing of the patterned mask comprises selectively removing the first mask layer before the performing of the third etching process and selectively removing the second mask layer after the performing of the third etching process, as taught by Mui. One having ordinary skill in the art is motivated to do so because, for example, further etch the trench to a farther depth in a controlled manner, increasing the capacitance of a subsequently formed capacitor in the trench.
Regarding claim 24, as explained above, Kuo discloses the limitations of claim 21.
Kuo further teaches, in FIG. 8A, the formation of a patterned hard mask 192 ([0045]: “In alternative embodiments, the etch mask 192 is a hard etch mask such as silicon oxide . . .”) over the substrate, wherein the forming of the hard mask implements the patterned hard mask as an etch mask ([0045]: “The openings of the etch mask 192 defines the regions for deep trenches” and [0046]: “Referring to FIG. 8B, the dielectric material layer 152 is patterned to form deep trenches 194 by a suitable etching process, such as wet etch, dry etch or a combination thereof). The examiner also notes that [0048] states: “In some embodiments, the deep trenches 150 are formed in the substrate 142 including silicon . . .” meaning that Kuo teaches the above described steps for etching into a silicon substrate.
Kuo does not explicitly teach that performing the etching process further etches the patterned hard mask.
Mui teaches, in Table Two, etching steps for rounding corners of a silicon substrate. Which have etching rates for both silicon and silicon oxide. The examiner notes that Kuo teaches a hard etch mask made of silicon oxide.
It would have been obvious to one having ordinary skill in the art at the effective filing date to conduct the etching process taught by Kuo such that the etchant is one of any of the etchants taught by Mui that further etch into silicon oxide (the material of the hard mask taught by Kuo). One having ordinary skill in the art is motivated to do so because, for example, the etchants taught by Mui in Table Two are well known, allowing for a precise etch and therefore an increase in yield (or, one is motivated to specifically motivated to select an etchant comprising fluorine and argon because “One of the plasma feed gas recipes which provides excellent results is a combination of CF.sub.4, HBr, and argon” as stated by Mui, paragraph 15, which further etches into the silicon oxide hard mask). See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:DeBrabander (US 10052875 B1) – FIG. D shows a mask 402 on top of a substrate (top surface thereof labeled 404) into which trench 420 is etched and rounded corners 422 are created.
Williams (US 6589879 B2) – Fluoride etchants used in trench formation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./ Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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