DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Potera (11152503, hereafter Potera) in view of Kong et al. (113471290, hereafter Kong).
Regarding claim 1, Potera discloses a vertical MOSFET comprising: a substrate (75, Fig. 8) having a first conductivity type; an epitaxially grown first layer (74, Fig. 8) grown over the substrate, the first layer having the first conductivity, the first layer being of a first semiconductor material having a first bandgap; a second layer (62, Fig. 8) of the first conductivity type over the first layer, … a first region (61, Fig. 8) of a second conductivity type formed over the second layer … a second region (66, Fig. 8) of the first conductivity type formed over the first region to create a source region (Col. 8, line 51) … a gate electrode (73a-73d, Fig. 8 insulated (78, Fig. 8) from the first region and configured to create an inversion layer in the first region when electrically biased above a threshold voltage to create a conductive path between the source region and the substrate (Col. 6, line 22-28); a source electrode (71, Fig. 8) contacting the source region; and a drain electrode (77, Fig. 8) contacting the substrate.
Potera fails to disclose the second layer being of a second semiconductor material having a second bandgap that is narrower than the first bandgap, an interface of the first layer and the second layer forming a heterojunction of the first conductivity type; … and [first and second regions above] being of the second semiconductor material.
However, Kong teaches the second layer (12, Fig. 2) being of a second semiconductor material having a second bandgap that is narrower than the first bandgap, an interface of the first layer and the second layer forming a heterojunction of the first conductivity type (p. 4, par. 2); … and [first and second regions above] being of the second semiconductor material (6/7, Fig. 2; p. 4, par2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Potera with Kong by providing a second layer with a narrower band gap than the first layer in order to realize the reverse of the device without turning on the MOSFET body PIN diode, restore functions, reduce costs, and improve device performance.
Regarding claim 2, Potera fails to disclose a MOSFET wherein the first semiconductor material is silicon carbide (SiC).
However, Kong teaches a MOSFET wherein the first semiconductor material is silicon carbide (SiC) (SiC, Fig. 2; p. 4, par. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Potera with Kong by implementing a first layer of silicon-carbide in order to provide high-voltage clocking capability and thermal conductivity
Regarding claim 3, Potera fails to disclose a MOSFET wherein the second semiconductor material is silicon (Si).
However, Kong teaches a MOSFET wherein the second semiconductor material is silicon (Si) (Si, Fig. 2; p. 4, par. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Potera with Kong by implementing a second material of silicon in order to provide high electron mobility that maximizes breakdown voltage and minimizes channel resistance.
Regarding claim 4, Potera fails to disclose a MOSFET wherein the first semiconductor material is silicon carbide (SiC) and the second semiconductor material is silicon (Si).
However, Kong teaches a MOSFET wherein the first semiconductor material is silicon carbide (SiC) and the second semiconductor material is silicon (Si) (Fig. 2; p. 4, par. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Potera with Kong by implementing a first material of silicon-carbide and second material silicon in order to provide high-voltage clocking capability and thermal conductivity with high electron mobility that maximizes breakdown voltage and minimizes channel resistance.
Regarding claim 5, Potera discloses a MOSFET wherein the first region (61, Fig. 8) forms a well layer (Col. 9, line 41).
Regarding claim 6, Potera discloses a MOSFET wherein the first region (61, Fig. 8) is a body region (Col. 9, line 41).
Regarding claim 7, Potera discloses a MOSFET wherein the first region (61, Fig. 8) forms a well layer (Col. 9, line 41) and wherein the gate electrode (73a-73d, Fig. 8) is formed in an insulated trench (63a-63d, Fig. 8; Col. 9, lines 35-37) in the second layer (62, Fig. 8), where the trench is at least partially filled with a conductive material (Col. 9, lines 38-39).
Regarding claim 8, Potera discloses a MOSFET wherein the first region (61, Fig. 8) forms a body region (Col. 9, line 41) and wherein the gate electrode (73a-73d, Fig. 8) is a planar gate electrode insulated from the body region (Col. 9, lines 37-39).
Regarding claim 9, Potera discloses a MOSFET further comprising a JFET layer in the first layer, the JFET layer comprising: JFET gate regions (72f, 72c, Fig. 8) of the second conductivity type and JFET channel regions (11a-11b, Fig. 1, Col. 4, line 20; Fig. 8, Col. 9, line 48) of the first conductivity type; and an electrical connector (64f, 64c, Fig. 8) electrically connecting the source electrode (71, Fig. 8) to the JFET gate regions; wherein the JFET channel regions are configured for conducting a vertical current when the MOSFET is in an on state (Col. 6, line 22-28).
Regarding claim 10, Potera discloses a MOSFET where the first region (61, Fig. 8) forms a well layer (Col. 9, line 41) and wherein the gate electrode (73a-73d, Fig. 8) is formed in an insulated first trench (78, 63a-63d, Fig. 8; Col. 9, line 35-37) in the second layer (62, Fig. 8), where the first trench is at least partially filled with a conductive material (Col. 9, line 38-39), wherein the electrical connector comprises a semiconductor contact region (64c, 64f, Fig. 8) of the second conductivity (Col. 8, line 65-66) type electrically connecting the source electrode (71, Fig. 8) to the JFET gate regions (72c, 72f, Fig. 8; Col. 10, line 10).
Regarding claim 11, Potera discloses a MOSFET wherein the contact region surrounds a second trench (64c, 64f, Fig. 8) that that does not contain the gate electrode (73a-73d, Fig. 8).
Regarding claim 12, Potera disclose a MOSFET wherein the second trench (64c/f, Fig. 8) is filled with the conductive material (Col. 9, line 27).
Regarding claim 13, Potera discloses a MOSFET where the first region (61, Fig. 8) forms a well layer (Col. 9, line 41) and wherein the gate electrode (73a-73d, Fig. 8) is formed in an insulated first trench (78/63a-63d, Fig. 8) in the second layer (62, Fig. 8), where the first trench is at least partially filled with a conductive material (Col. 9, line 38-39), wherein the electrical connector comprises a metal (col. 9, line 27) within a second trench (64c, 64f, Fig. 8) that electrically connects the source electrode (71, Fig. 8) to the JFET gate regions (72c, 72f, Fig. 8).
Regarding claim 14, Potera discloses a MOSFET where the first region (61, Fig. 8) forms a well layer (Col. 9, line 41) and wherein the gate electrode (73a-73d, Fig. 8) is formed in an insulated first trench (78/63a-63d, Fig. 8) in the second layer (62, Fig. 8), wherein the electrical connector is formed in a second trench (64c, 64f, Fig. 8) that does not contain the gate electrode.
Regarding claim 15, Potera discloses a MOSFET wherein the second trench (64c/f, Fig. 8) is deeper than the first trench (63a-63d, Fig. 8).
Regarding claim 16, Potera discloses a MOSFET wherein the JFET gate regions (64a-64) form a grid (Fig. 6), and a plurality of the gate electrodes (73a-73d) are formed in openings in the grid (Fig. 8).
Regarding claim 18, Potera discloses a MOSFET wherein the second layer (74, Fig. 8) is epitaxially grown over the first layer (Col. 9, line 17).
Regarding claim 19, a MOSFET wherein the second layer is bonded to the first layer is a product-by-process limitation. Applicant is reminded that "even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Accordingly, this limitation does not impart significant patentable weight to the claims.
Regarding claim 20, Potera discloses a method for forming a vertical MOSFET comprising: providing a substrate (75, Fig. 8) having a first conductivity type; epitaxially growing a first layer (74, Fig. 8; Col. 10, line 43) over the substrate, the first layer having the first conductivity, the first layer being of a first semiconductor material having a first bandgap, the first layer comprising SiC; providing a second layer (62, Fig. 8) of the first conductivity type over the first layer, …forming a first region (61, Fig. 8) of a second conductivity type formed over the second layer …forming a second region (66, Fig.8) of the first conductivity type formed over the first region to create a source region …forming a gate electrode (73a-73d, Fig. 8) insulated (78, Fig. 8) from the first region and configured to create an inversion layer in the first region when electrically biased above a threshold voltage to create a conductive path between the source region and the substrate (Col. 6, line 22-28); forming a source electrode (71, Fig. 8) contacting the source region; and forming a drain electrode (77, Fig. 8) contacting the substrate.
Potera fails to disclose the second layer being of a second semiconductor material having a second bandgap that is narrower than the first bandgap, the second layer comprising Si, an interface of the first layer and the second layer forming a heterojunction of the first conductivity type;…[first and second regions above] being of the second semiconductor material.
However, Kong teaches the second layer (12, Fig. 2) being of a second semiconductor material having a second bandgap that is narrower than the first bandgap, the second layer comprising Si, an interface of the first layer and the second layer forming a heterojunction of the first conductivity type (p. 4, par. 2);…[first and second regions above] being of the second semiconductor material (Fig. 2; p. 4, par. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Potera with Kong by providing silicon layers above silicon-carbide layers in order to realize the reverse of the device without turning on the SiC MOSFET body PIN diode, restore functions, reduce costs, and improve device performance.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Potera in view of Kong as applied to claim 1 above, and further in view of Hayashi (2022/0254915, hereafter Hayashi).
Regarding claim 17, Potera and Kong fail to disclose a MOSFET further comprising a third layer of the first conductivity type, the third layer forming an interface layer between the first layer and the second layer, the third layer having a first conductivity dopant concentration higher than a dopant concentration of the first layer and the second layer.
However, Hayashi teaches a MOSFET further comprising a third layer (21, Fig. 1) of the first conductivity type, the third layer forming an interface layer between the first layer (20, Fig. 1) and the second layer (2, Fig. 1), the third layer having a first conductivity dopant concentration higher than a dopant concentration of the first layer and the second layer (par. 0049).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Potera and Kong with Hayashi by providing a third layer between the first and second which has a higher impurity concentration than both layers in order to lower device’s internal on-resistance or prevent electrical breakdown and leakage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kouno (20230038806), particularly pertaining to the p-region well layer.
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/C.M.B./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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