Prosecution Insights
Last updated: July 17, 2026
Application No. 18/659,282

SEMICONDUCTOR ON INSULATOR WAFER WITH CAVITY STRUCTURES

Non-Final OA §102§103
Filed
May 09, 2024
Priority
Sep 22, 2020 — continuation of 12/027,580
Examiner
CRAWFORD EASON, LATANYA N
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Globalfoundries U.s. Inc.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
726 granted / 927 resolved
+10.3% vs TC avg
Minimal +0% lift
Without
With
+0.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
27 currently pending
Career history
966
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
83.4%
+43.4% vs TC avg
§102
10.6%
-29.4% vs TC avg
§112
3.7%
-36.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 927 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1, 2 & 4-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1,2 & 5-10 of U.S. Patent No. 12,027,580 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because: Regarding claim 1, A structure comprising: a substrate with at least one rectilinear cavity structure; a first insulator material sealing the at least one rectilinear cavity structure; a second insulator layer on the substrate and over the at least one rectilinear cavity structure; and a semiconductor material on the second insulator layer, wherein the first insulator material extends within an opening of the second insulator layer and is over and contacts the semiconductor material.(claim 1 of US Patent 12,027,580 B2) Regarding claim 2, wherein the at least one rectilinear cavity structure is lined with insulator material. (claim 2 of US Patent 12,027,580 B2) Regarding claim 4, further comprising a shallow trench isolation region formed in the semiconductor material above the second insulator layer and at least one wire on at least one of the semiconductor material above the at least one rectilinear cavity structure and the shallow trench isolation region. (claim 5 of US Patent 12,027,580 B2) Regarding claim 5, wherein the at least one rectilinear cavity structure is plural cavity structures of different dimensions.(claim 6 of US Patent 12,027,580 B2) Regarding claim 6, wherein the at least one rectilinear cavity structure is plural cavity structures of a same depth within the substrate.(claim 7 of US Patent 12,027,580 B2) Regarding claim 7, wherein the at least one rectilinear cavity structure is plural cavity structures separated from each other. (claim 8 of US Patent 12,027,580 B2) Regarding claim 8, wherein the at least one rectilinear cavity structure is a single rectilinear cavity with different depths. (claim 9 of US Patent 12,027,580 B2) Regarding claim 9, wherein the substrate is a single crystalline semiconductor material and the rectilinear cavity structure is bounded by the single crystalline semiconductor material and, at its top surface, the second insulator layer.(claim 10 of US Patent 12,027,580 B2) Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1,4,6,7,9, 10,11, & 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang (US Pub no. 2015/0145043 A1). Regarding claim 1,Huang et al discloses A structure comprising: a substrate (1001)with at least one rectilinear cavity structure(1051); a first insulator material(106/108) sealing the at least one rectilinear cavity structure(1051)[0028][0036]; a second insulator layer(1002) on the substrate (1001)and over the at least one rectilinear cavity structure(1051) [0028]; and a semiconductor material (1003)on the second insulator layer(1002), wherein the first insulator material(106/108 [0036]) extends within an opening of the second insulator layer (1002) and is over and contacts the semiconductor material element (1003) (fig. 1) . Regarding claim 4, Huang et al discloses further comprising a shallow trench isolation region(102) formed in the semiconductor material(1003) above the second insulator layer(1002) and at least one wire (109)on at least one of the semiconductor material above the at least one rectilinear cavity structure (1051)and the shallow trench isolation region(102)[0028][0036] fig. 1. Regarding claim 6, Huang et al discloses wherein the at least one rectilinear cavity structure (1051)is plural cavity structures of a same depth within the substrate(1001) fig. 1. Regarding claim 7, Huang et al discloses wherein the at least one rectilinear cavity structure (1051)is plural cavity structures separated from each other[0028] fig. 1. Regarding claim 9, Huang et al discloses wherein the substrate (1001)is a single crystalline semiconductor material [0038]and the rectilinear cavity structure(1051) is bounded by the single crystalline semiconductor material and, at its top surface, the second insulator layer(1002)[0037-0038] Regarding claim 10, Huang et al discloses A structure comprising: a substrate(1001) with at least one rectilinear cavity structure(1051) [0028] fig. 1; a first insulator material(106/108; 106 and 108 made of same material) [0036]sealing the at least one rectilinear cavity structure(1051) [0028] fig. 1; a second insulator layer (1002)on the substrate (1001)and over the at least one rectilinear cavity structure(1051) fig. 1[0028]; and a plurality of electrodes(109) contacting the first insulator material(106/108). Regarding claim 11, Huang et al discloses wherein the first insulator material (106/108)is over the second insulator layer (1002)and extends within an opening of the second insulator layer(1002)[0033] [0036]fig. 1. Regarding claim 13, wherein the plurality of electrodes(109) directly contacting the first insulator material(106/108) fig. 1. Claim(s) 10-17, 19 & 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Duqi (US Pub no. 2019/0375629 A1). Regarding claim 10, Duqi et al discloses A structure (fig. 10)comprising: a substrate (4)with at least one rectilinear cavity structure(2)[0020][0022]; a first insulator material (24)sealing the at least one rectilinear cavity structure(2) [0040-0041]; a second insulator layer (22)on the substrate(4) and over the at least one rectilinear cavity structure(2)[0038]; and a plurality of electrodes(28a/28b) contacting the first insulator material(24)[0044-0045]. Regarding claim 11, Duqi et al discloses wherein the first insulator material (24)is over the second insulator layer(22) and extends within an opening of the second insulator layer(22) (the first insulating material (24)l fill opening 16 of coating regions 18, since openings 16 is within peripheral insulating regions 22 the first insulator material 24 is within the periphery of element 22) fig. 10. Regarding claim 12, Duqi et al discloses wherein the at least one rectilinear cavity(2) structure is part of a microfluidic device fig. 10. Regarding claim 13, Duqi et al discloses wherein the plurality of electrodes(28a/28b) directly contacting the first insulator material(24) fig. 10. Regarding claim 14, Duqi et al discloses a structure comprising: a substrate(4) with at least one cavity structure(2) hermetically sealed with an insulator material(24); a buried insulator layer (22)on the substrate(4); and a semiconductor material(14) on the buried insulator layer (22)and above the at least one hermetically sealed cavity structure(2/20/32), and which contacts an underside of the insulator material(24). Regarding claim 15, Duqi et al discloses wherein the insulator material (24)extends within an opening of the buried insulator layer(22) (the first insulating material (24)l fill opening 16 of coating regions 18, since openings 16 is within peripheral insulating regions 22 the first insulator material 24 is within the periphery of element 22) fig. 10. Regarding claim 16, Duqi et al discloses wherein the at least one hermetically sealed cavity structure(2) comprises plural cavity structures(20/10a)[0071][0037]. Regarding claim 17, Duqi et al discloses wherein the at least one hermetically sealed cavity structure (2)comprises different heights(2/10a/20) fig. 10/fig. 3. Regarding claim 19, Duqi et al discloses further comprising an electrode(28a or 28b) above the at least one hermetically sealed cavity structure(2), which forms a microfluidic device[0030][0071]. Regarding claim 20, wherein the insulator material (24)contacts and is over the semiconductor material(14) fig. 10[0040-0041]. Claim(s) 14, 16, 17, 18, & 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang (US Pub no. 2021/0239647 A1) Regarding claim 14, Chang et al discloses a structure comprising: a substrate (230)with at least one cavity structure (244) hermetically sealed (anodic bonding [0057])with an insulator material(206)[0036]; a buried insulator layer (224)on the substrate(230); and a semiconductor material(208) on the buried insulator layer (224)and above the at least one hermetically sealed cavity structure(244), and which contacts an underside of the insulator material(206) fig. 2/fig. 24. Regarding claim 16, Chang et al discloses wherein the at least one hermetically sealed cavity structure(244) comprises plural cavity structures(240’) fig. 2/fig. 24[0036]. Regarding claim 17, Chang et al discloses wherein the at least one hermetically sealed cavity structure(244) comprises different heights fig. 2/fig. 24). Regarding claim 18, Chang et al discloses wherein the at least one hermetically sealed cavity structure (244)is lined with insulator material(242)[0036]. Regarding claim 19, Chang et al discloses further comprising an electrode (210)above the at least one hermetically sealed cavity structure(244), which forms a microfluidic device[0036]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2, 3, 5, & 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US Pub no. 2015/0145043 A1) in view of Meng (CN 108520864 A) Regarding claim 2, Huang et al discloses all the claim limitations of claim 1 but fails to teach, wherein the at least one rectilinear cavity structure is lined with insulator material. However, Meng et al discloses isolation layer 105 formed on an inner surface of a cavity (102) para 2 pp. 12. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Huang et al with the teachings of Meng et al such that wherein the at least one rectilinear cavity structure is lined with insulator material results to provide isolation from portions of the substrate. Regarding claim 3, Meng et al discloses wherein the insulator material (105) is thermal SiO₂ para 2 pp. 12. Regarding claim 5, Huang et al discloses all the claim limitations of claim 1 but fails to teach wherein the at least one rectilinear cavity structure is plural cavity structures of different dimensions. Meng et al discloses wherein the at least one rectilinear cavity structure(102) is plural cavity structures of different dimensions(fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Huang et al with the teachings of Meng et al to influence parasitic capacitance. Regarding claim 8, Meng et al discloses wherein the at least one rectilinear cavity structure (102)is a single rectilinear cavity with different depths fig. 1. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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Prosecution Timeline

May 09, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
79%
With Interview (+0.3%)
2y 8m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 927 resolved cases by this examiner. Grant probability derived from career allowance rate.

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