DETAILED ACTION
This application, 18/416151, attorney docket AD9667-US, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Taiwan Semiconductor Manufacturing Company, Ltd., and is a continuation of 17411416, filed 08/25/2021, now U.S. Patent # 11984261. 17411416 is a continuation of 16417797, filed 05/21/2019, now U.S. Patent # 11107630.16417797 claims priority from provisional application 62736734, filed 09/26/2018. Applicant’s election without traverse of invention group I, claims 1-15 in the reply filed on 6/2/2026 is acknowledged. Claims 16-20 have been cancelled by the applicant, and new claims 21-25 have been added.
Claims 1-15 and 21-25 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 10-15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 10 recites, “wherein a height of the upper piezoelectric region is less than a height of the lower piezoelectric region…” is indefinite because it is not clear if the measurement of a top surface from a common reference is being measures, or if the relative thickness is being claimed. There is no support for a height of the upper region less than a height of a lower region. The limitation, “length of the upper surface of the lower piezoelectric region is greater than the height of the upper piezoelectric region” is indefinite for the same reason.
Dependent claims include the defect of the parent claim .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 10, 11, 14, 15 and 21 are rejected under 35 U.S.C. 102 a1/a2 as being anticipated by Xiong et al., ( U.S. 2020/0091401.)
As for claim 1,
Xiong teaches in figures 7 and 8, an integrated chip, comprising:
a first conductive structure (17);
a second conductive structure (27) over the first conductive structure;
a dielectric structure (13) arranged between the first conductive structure and the second conductive structure, wherein the dielectric structure comprises an upper region (narrow width) over a lower region (wider region),
wherein the lower region comprises a first lateral surface and a second lateral surface on opposing sides of the upper region (at outer edges below the step); and
a passivation layer (22) over the second conductive structure and the dielectric structure, wherein the passivation layer comprises a lateral segment contacting the first lateral surface (stepped region below the top surface which covers the side faces), wherein
a height of the lateral segment is greater than a height of the upper region (lateral segment boundaries shown in annotated figure 8 below), and wherein a top surface of the lateral segment is below a top surface of the passivation layer (shown in figure 7).
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As for claim 2,
Xiong teaches the integrated chip of claim 1, and teaches that the top surface of the lateral segment is disposed above a bottom surface of the second conductive structure. (shown in figure 7)
As for claim 3,
Xiong teaches the integrated chip of claim 1, wherein a height of the passivation layer directly over a center of the second conductive structure is greater than the height of the upper region (shown in figure 7 where the length is half of L14-L13).
As for claim 4,
Xiong teaches the integrated chip of claim 1, wherein a length of the first lateral surface is greater than the height of the upper region. (shown in figure 7)
As for claim 5,
Xiong teaches the integrated chip of claim 4, further comprising:
a conductive contact (44a) over the passivation layer and comprising a protrusion extending through the passivation layer to a top surface of the second conductive structure (24), wherein a width of the protrusion is greater than the length of the first lateral surface.
As for claim 6,
Xiong teaches the integrated chip of claim 1, wherein the passivation layer comprises a vertical segment arranged along a sidewall of the second conductive structure, wherein a lateral thickness of the vertical segment defined along the sidewall of the second conductive structure is less than the height of the lateral segment. (shown in figure 7. The height includes a thickness, so must be less than height.)
As for claim 10,
Xiong teaches an integrated chip, comprising:
a bottom electrode (17)over a substrate (4);
a top electrode (27) over the bottom electrode;
a piezoelectric structure (13) between the bottom electrode and the top electrode, wherein the piezoelectric structure comprises an upper piezoelectric region over a lower piezoelectric region (regions above and below the step),
wherein a height of the upper piezoelectric region is less than a height of the lower piezoelectric region (Heights in Xiong are similar so instant application. See §112b rejection, above);
and a dielectric layer (22) over the piezoelectric structure and the top electrode, wherein the dielectric layer directly contacts an upper surface of the lower piezoelectric region (at the step),
wherein a length of the upper surface of the lower piezoelectric region is greater than the height of the upper piezoelectric region.(the length of the step into the page is greater than the thickness.)
As for claim 11,
Xiong teaches the integrated chip of claim 10, wherein the upper piezoelectric region is in physical contact with the lower piezoelectric region. (They are formed from one material layer)
As for claim 14,
Xiong teaches the integrated chip of claim 10, wherein a height of the top electrode is greater than the height of the upper piezoelectric region,
wherein the length of the upper surface of the lower piezoelectric region is greater than the height of the top electrode. (shown in figure 7)
As for claim 15,
Xiong teaches the integrated chip of claim 10, wherein the upper surface of the lower piezoelectric region laterally wraps around an outer perimeter of the upper piezoelectric region (shown in figure 6 where the dashed line shows the step all around the upper portion.)
As for claim 21,
Xiong teaches an integrated chip, comprising:
a first conductive structure (17) over a substrate (5);
a dielectric structure (13)over the first conductive structure, wherein the dielectric structure comprises a lower region (wider portion) and an upper region (narrower portion) , wherein the lower region comprises a lateral surface (outer sidewalls) disposed below a top surface of the upper region;
a second conductive structure (27) over the upper region of the dielectric structure; and
a passivation layer (22) over the second conductive structure and the dielectric structure, wherein the passivation layer comprises a lateral segment interfacing with the lateral surface of the lower region (lowest step, shown in annotated figure above) , wherein a top surface of the lateral segment is disposed between a bottom surface of the second conductive structure and a top surface of the second conductive structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Xiong in view of Zuo et al. (U.S. 2013/0214643).
As for claim 7,
Xiong teaches the integrated chip of claim 1, but does not teach that the lower region of the dielectric structure comprises a first piezoelectric material and the upper region of the dielectric structure comprises a second piezoelectric material different from the first piezoelectric material.
However, Zuo teaches a composite Piezoelectric element using different upper and lower piezo materials in figure 2.
It would have been obvious to one skilled in the art at the effective filing date of this application use the laminate of Zuo in the structure of Xiong to form a laterally vibrating resonator with a high energy conversion. Zuo [0002,0004]. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 8, 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Xiong.
As for claim 8,
Xiong teaches the integrated chip of claim 1, does not teach a height of the lower region is greater than a vertical distance between the first lateral surface and a top surface of the second conductive structure.
However, the vertical distance between the first lateral surface and a top surface of the second conductive structure is a result dependent variable that depends on the thicknesses of the upper portion of 13 and the thickness of the electrode and barrier, which are dependent on the amount of static charge being controlled and the electrical power requirement of the device, respectively. Therefore, It would have been obvious to one skilled in the art at the effective filing date of this application adjust the thicknesses to the claimed ratio. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 12,
Xiong teaches the integrated chip of claim 10, wherein the upper surface of the lower piezoelectric region extends from a sidewall of the upper piezoelectric region to a sidewall of the lower piezoelectric region (shown in figure 7),
But does not teach that a length of an upper surface of the bottom electrode (17) extending from the sidewall of the lower piezoelectric region to a sidewall of the bottom electrode is less than the length of the upper surface of the lower piezoelectric region.
However, the length of the step surface of the lower portion is result dependent variable that adjust the amount of static charge being controlled. Therefore, it would have been obvious to one skilled in the art at the effective filing date of this application adjust the step size to the claimed ratio. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 13,
Xiong makes obvious the integrated chip of claim 12, and teaches that a height of the dielectric layer directly over the upper surface of the lower piezoelectric region discretely increases from the sidewall of the lower piezoelectric region at a first point in a first direction towards the sidewall of the upper piezoelectric region (it increases as a step),
wherein the height of the dielectric layer continuously increases from the first point in the first direction (there are no discontinuities).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Xiong in view of Yanase et al. (U.S. 20070247260).
As for claim 9,
Xiong teaches the integrated chip of claim 1, but does not teach a thickness of the passivation layer is within a range of approximately 0.1 micrometers (um) to 0.3 um.
However, Yanase teaches a passivation of 01 um [0046].
It would have been obvious to one skilled in the art at the effective filing date of this application to use a thickness of 0.1 um because passivation thickness is a result dependent variable the is selected to provide isolation from the environment or moisture and can modify the resonance characteristics of the device. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Xiong in view of Lee et al. (U.S. 2018/0062608).
As for claim 22,
Xiong teaches the integrated chip of claim 21, further comprising:
a conductive contact (44A) over the passivation layer, wherein the conductive contact comprises a protrusion extending through the passivation layer to contact the second conductive structure,
But does not teach that the conductive contact comprises a slanted vertical segment directly overlying at least a portion of the lateral surface of the lower region.
However, Lee teaches in figure 1, the conductive contact (150, right side) comprises a slanted vertical segment directly overlying at least a portion (stepped area of 140) of the lateral surface of the lower region.
It would have been obvious to one skilled in the art at the effective filing date of this application use the slanted contacts of Lee in the device of Xiong because the slanted layers reduce sharp edges that create stress fractures. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 23,
Xiong in view of Lee makes obvious the integrated chip of claim 22, wherein a height of a segment of the passivation layer directly contacting a sidewall of the protrusion is greater than a height of the upper region. (passivation layer contacts the contact above the upper portion)
As for claim 24,
Xiong in view of Lee makes obvious the integrated chip of claim 22, wherein a lateral distance between an outer sidewall of the upper region and the protrusion is less than a width of the protrusion. (approx. half of L13-L24)
As for claim 25,
Xiong in view of Lee makes obvious the integrated chip of claim 21, but does not teach that the passivation layer comprises a slanted vertical segment extending from the lateral segment to a sidewall of the second conductive structure, wherein the slanted vertical segment directly contacts an outer edge of the second conductive structure in contact with the upper region.
However, Lee teaches in figure 19, the passivation layer (160) comprises a slanted vertical segment extending from the lateral segment to a sidewall of the second conductive structure, wherein the slanted vertical segment directly contacts an outer edge of the second conductive structure in contact with the upper region. (shown on right of structure, Lee has the contacts on opposite sides, so the upper contact is on the right of figure 19 of Lee).
It would have been obvious to one skilled in the art at the effective filing date of this application use the slanted contacts of Lee in the device of Xiong because the slanted layers reduce sharp edges that create stress fractures. One skilled in the art would have combined these elements with a reasonable expectation of success.
Conclusion
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893
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