DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on May 09, 2024 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-8, and 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2023/0245888 A1).
Claim 1, Kim discloses a method of forming an epitaxial stack (structure 100 includes a superlattice of Si layers 130 and SiGe layers 140 in an epitaxial stack, hereinafter, epitaxial stack 130/140, [0080], Fig. 1), the method comprising:
providing a substrate (substrate 110, [0080], Fig. 1) to a process chamber (substrate is provided to reaction chamber 204 which is a process chamber, hereinafter, process chamber 204, [0082], Figs. 1 and 2),
performing a plurality of deposition cycles (method comprises executing one or more deposition cycles, [0044], Figs. 1 and 2), thereby forming the epitaxial stack 130/140 on the substrate 110 (deposition cycles forms the epitaxial stack 130/140 on the substrate 110, [0044], Figs. 1 and 2), the epitaxial stack 130/140 comprising a plurality of first epitaxial pairs (epitaxial stack 130/140 comprises a plurality of first epitaxial pairs (i.e. each pair of a single Si layer 130 and single SiGe layer 140 are first epitaxial pairs, hereinafter, first epitaxial pairs 130/140_1), [0044], Figs. 1 and 2), wherein each first epitaxial pair 130/140_1 comprises a first epitaxial layer (first epitaxial pairs 130/140_1 further includes a single Si layer 130 which is a first epitaxial layer, hereinafter, first epitaxial layer 130, [0044], Figs. 1 and 2) and a second epitaxial layer (first epitaxial pairs 130/140_1 further includes a single SiGe layer 140 which is a second epitaxial layer, hereinafter, second epitaxial layer 140, [0044], Figs. 1 and 2), wherein the first epitaxial layer 130 and the second epitaxial layer 140 of each first epitaxial pair 130/140_1 comprises at least a first Group-IV semiconductor material (first epitaxial layer 130 and the second epitaxial layer 140 of each first epitaxial pair 130/140_1 comprises at least a first Group-IV semiconductor material (i.e. Si), [0080], Fig. 1) and the second epitaxial layer 140 of each first epitaxial pair 130/140_1 further comprises a second Group-IV semiconductor material being different from the first Group-IV semiconductor material (second epitaxial layer 140 of each first epitaxial pair 130/140_1 further comprises a second Group-IV semiconductor material (i.e. SiGe) being different from the first Group-IV semiconductor material (i.e. Si), [0080], Fig. 1),
wherein each of the plurality of deposition cycles is performed at a pressure value of less than 10 Torr (reaction chamber 204 is maintained at a pressure of at least 5 Torr to 10 Torr, [0006], Figs. 1 and 2).
Claim 2, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 1.
Kim discloses wherein each of the plurality of deposition cycles (method comprises executing one or more deposition cycles, [0044], Figs. 1 and 2) is performed at a pressure value in a range of about 1 Torr to about 5 Torr (each of the plurality of deposition cycles is performed at a pressure value in a range of about 5 Torr, [0006] and [0093], Figs. 1 and 2).
Claim 3, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 1.
Kim discloses wherein each deposition cycle of the plurality of deposition cycles (method comprises executing one or more deposition cycles, [0044], Figs. 1 and 2) comprises:
a first deposition pulse comprising providing a first Group-IV semiconductor material (i.e. Si) precursor gas (first deposition pulse provides a first Group-IV semiconductor material precursor gas containing a silicon (Si) precursor (i.e. silane or halosilane), [0077], Figs. 1 and 2)), thereby forming the first epitaxial layer 130 (first deposition pulse of a first Group-IV semiconductor material precursor gas containing a silicon (Si) precursor (i.e. silane or halosilane) forms the first epitaxial layer 130, [0077], Figs. 1 and 2)), and
a second deposition pulse comprising providing the first Group-IV semiconductor material (i.e. Si) precursor gas (second deposition pulse provides a first Group-IV semiconductor material precursor gas containing a silicon (Si) precursor (i.e. silane or halosilane), [0077], Figs. 1 and 2)) and further comprising providing a second Group-IV semiconductor material (i.e. SiGe) precursor gas (second deposition pulse further comprising providing a second Group-IV semiconductor material precursor gas containing a germanium (Ge) precursor (i.e. germane), [0077], Figs. 1 and 2)), thereby forming the second epitaxial layer 140 (second deposition pulse further comprising providing a first Group-IV semiconductor material precursor gas containing a silicon (Si) precursor (i.e. silane or halosilane) and a second Group-IV semiconductor material precursor gas containing a germanium (Ge) precursor (i.e. germane) to form the second epitaxial layer 140, [0077], Figs. 1 and 2)), wherein the second Group-IV semiconductor material precursor gas (silane or halosilane silicon precursor gas and germane germanium precursor gas are the second Group-IV semiconductor material precursor gas, [0077], Figs. 1 and 2) is different from the first Group-IV semiconductor material (i.e. Si) precursor gas (germane germanium precursor gas in the second Group-IV semiconductor material precursor gas is different from the silane or halosilane silicon precursor gas in the first Group-IV semiconductor material precursor gas, [0077], Figs. 1 and 2).
Claim 4, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 1.
Kim discloses wherein each deposition cycle further comprises a purge pulse comprising providing a first Si-containing precursor gas and providing a hydrogen halide gas (purge pulse of halosilane comprises providing the first Si-containing precursor gas and providing a hydrogen halide gas, [0068], Figs. 1 and 2).
Claim 6, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 4.
Kim discloses wherein the provision of the first Si-containing precursor gas and the provision of the hydrogen halide gas is done during an overlapping period (provision of the first Si-containing precursor gas and the provision of the hydrogen halide gas (i.e. halosilane) is done during an overlapping period, [0044], Figs. 1 and 2).
Claim 7, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 4.
Kim discloses wherein the first Si-containing precursor gas and the hydrogen halide gas comprises chlorine (first Si-containing precursor gas and the hydrogen halide gas comprising chlorine include chlorosilanes, [0052], Figs. 1 and 2).
Claim 8, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 4.
Kim discloses wherein the first Si-containing precursor gas is a chlorosilane (first Si-containing precursor gas is a chlorosilanes, [0052], Figs. 1 and 2).
Claim 13, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 3.
Kim discloses wherein during each deposition cycle the first Group-IV semiconductor material precursor gas is provided in a continuous flow (during each deposition cycle the first Group-IV semiconductor material precursor gas (i.e. dichlorosilane) is provided in a continuous flow, [0093], Figs. 1 and 2) and wherein the second Group-IV semiconductor material precursor gas is provided intermittently (second Group-IV semiconductor material precursor gas is provided intermittently for each layer containing germanium, [0093], Figs. 1 and 2).
Claim 14, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 3.
Kim discloses wherein the first Group-IV semiconductor material precursor gas (i.e. dichlorosilane) comprises substantially a second Si-containing precursor gas and the second Group-IV semiconductor material precursor gas comprises substantially a Ge-containing precursor gas (the first Group-IV semiconductor material precursor gas (i.e. dichlorosilane) comprises substantially a second Si-containing precursor gas and the second Group-IV semiconductor material precursor gas comprises substantially a Ge-containing precursor gas, [0093], Figs. 1 and 2).
Claim 15, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 14.
Kim discloses wherein the second Si-containing precursor gas is a silane and the Ge-containing precursor gas is a germane (second Si-containing precursor gas is a silane and the Ge-containing precursor gas is a germane, [0093], Figs. 1 and 2)).
Claim 16, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 14.
Kim discloses wherein the second Si-containing precursor gas is di-silane and the Ge-containing precursor gas is mono-germane (second Si-containing precursor gas is di-silane and the Ge-containing precursor gas is mono-germane, [0093], Figs. 1 and 2).
Claim 17, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 16.
Kim discloses wherein the second Si-containing precursor gas is provided with a flow in a range of 30 sccm to 600 sccm (second Si-containing precursor gas is provided with a flow in a range of 50 sccm to 300 sccm, [0093], Figs. 1 and 2) and the Ge-containing precursor gas is provided with a flow in a range of 100 sccm to 1600 sccm (Ge-containing precursor gas is provided with a flow in a range of 100 sccm to 300 sccm, [0093], Figs. 1 and 2).
Claim 18, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 17.
Kim discloses wherein the second Si-containing precursor gas is provided with a flow in a range of 30 sccm to 100 sccm during the first deposition pulse (second Si-containing precursor gas is provided with a flow in a range of 30 sccm to 100 sccm during the first deposition pulses, [0093], Figs. 1 and 2) and in a range of 50 sccm to 100 sccm during the second deposition pulse (second Si-containing precursor gas is provided with a flow in a range of 50 sccm to 100 sccm during the second deposition pulses, [0093], Figs. 1 and 2).
Claim 19, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 1.
Kim discloses wherein the epitaxial stack 130/140 further comprises a second epitaxial pair 130/140_3, the second epitaxial pair being different than the first epitaxial pair (epitaxial stack 130/140 further comprises a second epitaxial pair 130/140_3, the second epitaxial pair being different than the first epitaxial pair, when the concentration of x in Si1-xGex may vary between layers, [0036], Figs. 1 and 2) and wherein the epitaxial stack is formed on the substrate 110 with at least one second epitaxial pair 130/140_2 being in between two neighboring first epitaxial pairs 130/140 (epitaxial stack is formed on the substrate 110 with at least one second epitaxial pair 130/140_2 being in between two neighboring first epitaxial pairs 130/140, [0040], Figs. 1 and 2).
Claim 20, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 19.
Kim discloses wherein the second epitaxial pair 130/140_2 comprises the first epitaxial layer 130 and a third epitaxial layer 140, the third epitaxial layer 140 comprising the at least first Group-IV semiconductor material and further comprising the second Group-IV semiconductor material (third epitaxial layer 140 comprises a first Group-IV semiconductor material precursor gas containing a silicon (Si) precursor (i.e. silane or halosilane) and a second Group-IV semiconductor material precursor gas containing a germanium (Ge) precursor (i.e. germane), [0077], Figs. 1 and 2)), wherein the plurality of the first epitaxial pairs 130/140_1 has a first concentration of the second Group-IV semiconductor material (i.e. SiGe) and a third epitaxial pair 130/140_3 has a second concentration of the second Group-IV semiconductor material (i.e. SiGe), the second concentration being different than the first concentration (each epitaxial pair 130/140 may have a different concentration of the second Group-IV semiconductor material (i.e. as long as the total concentration of 99.999% atomic percent of Si and Ge is maintained), [0049], Figs. 1 and 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of More (US 2022/0102496 A1).
Claim 5, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 4.
Kim does not explicitly disclose wherein the purge pulse is performed for a pre-determined duration before and after each deposition.
However, More discloses wherein the purge pulse is performed for a pre-determined duration before and after each deposition (More, fifth etching process is a purge pulse and may be performed for a pre-determined duration before and after each deposition, [0074], Fig. 20; Kim, epitaxial stack 130/140, [0080], Fig. 1). The combination to utilize a dry etchant for a pre-determined duration before and after each deposition prepares the surface for optimal deposition (More, [0074]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a dry etchant for a pre-determined duration before and after each deposition to prepare the surface for optimal deposition (More, [0074]).
Claim 9, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 4.
Kim discloses wherein the first Si-containing precursor gas is di-chlorosilane (first Si-containing precursor gas is di-chlorosilane, [0052], Figs. 1 and 2).
Kim does not explicitly disclose wherein the hydrogen halide gas is hydrogen chloride.
However, More discloses wherein the hydrogen halide gas is hydrogen chloride (More, halogen chloride (HCl) gas, [0074], Fig. 20; Kim, chlorine, [0083], Figs. 1 and 2). The combination to utilize a dry etchant for a pre-determined duration before and after each deposition prepares the surface for optimal deposition (More, [0074]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a dry etchant for a pre-determined duration before and after each deposition to prepare the surface for optimal deposition (More, [0074]).
Claim 10, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 4.
Kim does not explicitly disclose wherein a ratio of flow of the first Si-containing precursor gas to flow of the hydrogen halide gas is about 1:1.
However, More discloses wherein a ratio of flow of the first Si-containing precursor gas to flow of the hydrogen halide gas is about 1:1 (More, ratio of flow of the first Si-containing precursor gas to flow of the hydrogen halide gas is about 1:1 as flow rate of the hydrogen halide gas is approximately between 50 and 300 sccm, [0074], Fig. 20; Kim, ratio of flow of the first Si-containing precursor gas to flow of the hydrogen halide gas is about 1:1 as flow rate of the first Si-containing precursor gas is in a range of 50 sccm to 300 sccm, [0093], Figs. 1 and 2). The combination to utilize a precursor gas and hydrogen halide gas at a specific flow rate during each deposition prepares the surface for optimal deposition (More, [0074]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a dry etchant for a pre-determined duration before and after each deposition to prepare the surface for optimal deposition (More, [0074]).
Claim 11, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 10.
Kim discloses wherein the flow of the first Si-containing precursor gas and the flow of the hydrogen halide gas is about 300 sccm (More, flow of the first Si-containing precursor gas and the flow of the hydrogen halide gas is about 300 sccm, [0074], Fig. 20; Kim, flow of the first Si-containing precursor gas and the flow of the hydrogen halide gas is about 300 sccm, [0093], Figs. 1 and 2).
Claim 12, Kim discloses the method (epitaxial stack 130/140, [0080], Fig. 1) according to claim 5.
Kim does not explicitly disclose wherein the pre-determined duration is about 5 seconds.
However, More discloses wherein the pre-determined duration is about 5 seconds (More, fifth time may be approximately 5 seconds, [0074], Fig. 20; Kim, Figs. 1 and 2). The combination to utilize a pre-determined duration is about 5 seconds during each deposition prepares the surface for optimal deposition (More, [0074]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a dry etchant for a pre-determined duration before and after each deposition to prepare the surface for optimal deposition (More, [0074]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miskin (US 2023/0005744 A1) discloses a method of manufacturing a semiconductor device including silicon and silicon-germanium, providing a substrate 302 to a process chamber 102, performing a plurality of deposition cycles of a silicon-containing precursor 142, a germanium-containing precursor 146, a halide 152, and a purge gas 158 ([0042], Fig. 1), wherein each of the plurality of deposition cycles is performed at a pressure value of less than 10 Torr (i.e. 1 Torr to 10 Torr, [0011]).
Khazaka (US 2022/0364262 A1) discloses a method of manufacturing a semiconductor device including silicon and silicon-germanium, providing a substrate 200 to a process chamber 304, performing a plurality of deposition cycles of a silicon-containing precursor , a germanium-containing precursor, and a purge gas, wherein each of the plurality of deposition cycles is performed at a pressure value of at least 5 Torr to 10 Torr.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812