DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/26/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election with traverse of claims 1-12 and withdrawal of claims 13-20 in the reply filed on 7/16/2024 is acknowledged. Basis of traversal is that claims 1-12 directed to the superlattice structure that is not etched before the formation of the plurality of nanosheets and claims 13-20 directed to the superlattice structure that is etched before the formation of the plurality of nanosheets are considered obvious variants (page 8 of 11). As such, the withdrawn claims 13-20 are rejoined and Claims 1-20 are being examined. Claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-12, 13-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 13, Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “gate” is used by the claim to mean “dummy gate or dummy poly gate” while the accepted meaning is “non-dummy, non-replacement, or non-sacrificial.” The term is indefinite because while the specification describes the gate as a “dummy gate” or “dummy poly gate” as described in paragraph [0030], it is replaced with only “gate” in the claims 1 and 13. Compared to the meaning consistency of “dummy dielectric interlayers” present in both disclosure (¶ [0044]) and claims (1, 13, and others), the “dummy gate” has inconsistently shifted from “dummy gate” in disclosure to only “gate” in claims. While the functioning of the “gate” in claims (1, 13) has not changed from meaning “dummy gate or dummy poly gate” the wording has shifted from “sacrificial or replacement” to “non-sacrificial or non-replacement”, which is inconsistent and can cause confusion. As such, to preserve the consistent functioning of the dummy gate, which is sacrificial and replacement, the “gate” in claims 1, 13 will be best understood as the “dummy gate” and examined as such.
Regarding claims 2-12 and 14-20, the claims are similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-17, 1-5, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable by Cheng (US 20200266060 A1) in view of Ando (US 10236217 B1)
Regarding claim 13, Cheng discloses A method (¶ [0001]) of forming a semiconductor device, the method comprising:
(Fig. 2, ¶¶ [0044, 0046]) forming a superlattice structure (alternating 111, 113, 115, 117 and 112, 114, 116) on a substrate (100), the superlattice structure comprising a plurality of first layers (111, 113, 115, 117) of a first material (silicon germanium) and a corresponding plurality of second layers (112, 114, 116) of a second material (silicon oxide, ¶ [0037]), the plurality of first layers and the plurality of second layers being alternatingly arranged in a plurality of stacked pairs;
Cheng does not disclose forming gate and gate spacers on the unetched continuous superlattice but instead disclose etching the superlattice structure (Fig. 3A, ¶ [0049]) before forming the gate and gate spacers (Fig. 4B, ¶ [0052]).
Ando in the same field of endeavor discloses (Fig. 1) a superlattice structure with alternating layers (105a – 105d, 107a-107d) and
(Ando: Fig. 2) forming one or more gate (110) and gate spacers (130) in a gate region on the substrate and the superlattice structure;
(Ando: Fig. 3) etching the superlattice structure between the one or more gate and gate spacers to form an etched superlattice structure, and to form one or more source regions and one or more drain regions (S/D Region);
Cheng discloses forming dummy gates and dummy gate spacers on an etched superlattice instead of on an unetched superlattice, and Ando discloses forming the dummy gate and dummy gate spacers on unetched superlattice. While both methods of forming dummy gates on etched superlattice and forming dummy gates on an unetched superlattice, then etching offer both advantages and challenges, artisans in the art would have appreciated one advantage of forming dummy gates on an unetched superlattice is simpler and because the dummy gate is formed over the full superlattice structure before etching, ensuring consistent dielectric and metal coverage. As such one of ordinary skill in the art before the effective filing date of the invention would have selected to form the dummy gate and dummy gate spacers on the superlattice, then etching to form other parts for a diversity of design choices as taught by Ando to substitute for the method of Cheng for a diversity of application.
The modified method of Cheng-Ando would result in the structure to be ready for the next steps as disclosed by Cheng as follow:
(Fig. 5, ¶ [0057]) forming a plurality of nanosheets from the etched superlattice structure, the plurality of nanosheets (112, 114, 116) separated by a corresponding plurality of voids (110-R) between each nanosheet;
(Fig. 7, ¶ [0060]) filling the corresponding plurality of voids with a plurality of dummy dielectric interlayers (137);
(Fig. 9, ¶ [0065]) forming an inner spacer (138) on the plurality of dummy dielectric interlayers; and
(Fig. 10, ¶ [0067]) depositing a source material (150) in the one or more source regions and a drain material (150) in the one or more drain regions.
Regarding claim 14, Cheng in view of Ando discloses the method of claim 13. Cheng further discloses wherein a top layer of the superlattice structure is one of the plurality of first layers (117, Fig. 4B), the plurality of first layers comprising silicon germanium (¶ [0046]), and the plurality of second layers comprising silicon oxide (¶ [0037]).
Regarding claim 15, Cheng in view of Ando discloses the method of claim 13. Cheng further discloses wherein the plurality of dummy dielectric interlayers (137, Fig) comprises silicon oxide (¶ [0075]).
Regarding claim 16, Cheng in view of Ando discloses the method of claim 15. Cheng further discloses comprising removing the plurality of dummy dielectric interlayers (137) after depositing the source material and the drain material (¶ [0076]).
Regarding claim 17, Cheng in view of Ando discloses the method of claim 13. Cheng further discloses wherein the first material of the plurality of first layers comprises silicon germanium and the second material of the plurality of second layers comprises silicon (¶ [0046]), or the first material of the plurality of first layers comprises silicon and the second material of the plurality of second layers comprises silicon germanium.
Regarding claim 1, Cheng discloses A method ¶ [0004]) of forming a semiconductor device, the method comprising:
(Fig. 2, ¶ [0046]) forming a superlattice structure (110) on a substrate (100), the superlattice structure comprising a plurality of first layers (111, 113, 115, 117) of a first material (SiGe) and a corresponding plurality of second layers (112, 114, 116) of a second material (Si), the plurality of first layers and the corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs;
Cheng does not disclose forming gate and gate spacers on the unetched continuous superlattice but instead disclose etching the superlattice structure (Fig. 3A, ¶ [0049]) before forming the gate and gate spacers (Fig. 4B, ¶ [0052]).
Ando in the same field of endeavor discloses (Fig. 1) a superlattice structure with alternating layers (105a – 105d, 107a-107d) and
(Ando: Fig. 2) forming one or more gate (110) and gate spacers (130) in a gate region on the substrate and the superlattice structure;
(Ando: Fig. 3) etching the superlattice structure between the one or more gate and gate spacers to form an etched superlattice structure, and to form one or more source regions and one or more drain regions (S/D Region);
Cheng discloses forming dummy gates and dummy gate spacers on an etched superlattice instead of on an unetched superlattice, and Ando discloses forming the dummy gate and dummy gate spacers on unetched superlattice. While both methods of forming dummy gates on etched superlattice and forming dummy gates on an unetched superlattice, then etching offer both advantages and challenges, artisans in the art would have appreciated one advantage of forming dummy gates on an unetched superlattice is simpler and because the dummy gate is formed over the full superlattice structure before etching, ensuring consistent dielectric and metal coverage. As such one of ordinary skill in the art before the effective filing date of the invention would have selected to form the dummy gate and dummy gate spacers on the superlattice, then etching to form other parts for a diversity of design choices as taught by Ando to substitute for the method of Cheng for a diversity of application.
The modification method of Cheng-Ando would result in an etched superlattice structure ready to form nanosheets and voids on the etched superlattice described by Cheng as follow:
(Fig. 5, ¶ [0057]) forming a plurality of nanosheets (112, 114, 116) from the superlattice structure, the plurality of nanosheets separated by a corresponding plurality of voids (110-R) between each nanosheet;
(Fig. 7, ¶ [0059]) filling the corresponding plurality of voids with a plurality of dummy dielectric interlayers (137);
However, the invention claims the etching step on the superlattice structure is done after forming the nanosheets and the voids.
As admitted by the Applicant in the Remark of record mailed on 7/16/2026, forming nanosheets and voids on unetched superlattice or on etched superlattice are obvious variants. As such one of ordinary skill in the art before the effective filing date of the invention would have substituted the sequence steps of Cheng-Ando with the sequence steps of the obvious variants to form the nanosheets and voids on unetched superlattice structure before etching it to form S/D regions.
Thus the modified process of Cheng-Ando-obvious variants would result in a structure on unetched superlattice that is ready for the next steps:
(Cheng: this step is moved to after forming dummy gate, nanosheets, void, Fig. 3A, ¶ [0049]) etching the plurality of nanosheets between the one or more gate and gate spacers to form one or more source regions and one or more drain regions (S/D regions, Fig. 5);
(Fig. 9, ¶ [0065]) forming an inner spacer (138) on the plurality of dummy dielectric interlayers; and
(Fig. 10, ¶ [0067]) depositing a source material in the one or more source regions (150) and a drain material (150) in the one or more drain regions.
Regarding claim 2, Cheng in view of Ando discloses the method of claim 1. Cheng further discloses wherein a top layer of the superlattice structure is one of the plurality of first layers (117, Fig. 3B, the plurality of first layers comprising silicon germanium (¶ [0046]), and the plurality of second layers comprising silicon (¶ [0046]).
Regarding claim 3, Cheng in view of Ando discloses the method of claim 1. Cheng further discloses wherein the plurality of dummy dielectric interlayers comprises silicon oxide ¶ [0075]).
Regarding claim 4, Cheng in view of Ando discloses the method of claim 3. Cheng further discloses comprising removing the plurality of dummy dielectric interlayers after depositing the source material and the drain material (Fig. 12A, ¶ [0077])
Regarding claim 5, Cheng in view of Ando discloses the method of claim 1. Cheng further discloses wherein the first material of the plurality of first layers comprises silicon germanium and the second material of the plurality of second layers comprises silicon (¶ [0046]), or the first material of the plurality of first layers comprises silicon and the second material of the plurality of second layers comprises silicon germanium.
Regarding claim 12, Cheng in view of Ando discloses the method of claim 1. Cheng further discloses comprising forming a replacement metal gate (174, Fig. 12A, ¶ [0077]) in the gate region and forming a contact (140, Fig. 12A, ¶ [0069]) on one or more of the source material and one or more of the drain material.
Claim(s) 6-8,11,18 is/are rejected under 35 U.S.C. 103 as being unpatentable by Cheng (US 20200266060 A1) in view of Ando (US 10236217 B1) and Hsu (US 20220093472 A1)
Regarding claim 6, Cheng in view of Ando discloses the method of claim 1. Cheng further discloses wherein forming the plurality of nanosheets from the superlattice structure comprises: selectively etching the superlattice structure to form the plurality of nanosheets and the corresponding plurality of voids (Fig. 5, ¶ [0057]), the plurality of nanosheets comprising the second material (Si, ¶ [0046]);
Cheng is silent regarding depositing a cladding material around each of the plurality of nanosheets; dry oxidizing the plurality of nanosheets to form a plurality of oxide layers surrounding the cladding material; and annealing the plurality of nanosheets to remove the second material to form the plurality of nanosheets comprising the cladding material.
Hsu, in the same field of endeavor, discloses a superlattice (nanosheet device, ¶ [0003]) forming nanosheet channels (215, Fig. 2B) and voids (277, Fig. 2B) wherein cladding (116) deposited on the channel layer (215) (operation 104, ¶ [0028]); dry oxidizing (the interfacial layer 280 is formed by any of the processes described herein, such as thermal oxidation, chemical oxidation, ALD, CVD, other suitable process, ¶ [0034]) the plurality of nanosheets to form a plurality of oxide layers surrounding the cladding material (280, ¶ [0034]); and annealing (thermal drive-in to move elements in cladding 216 into the channel 215, operation 107, ¶ [0032]) the plurality of nanosheets to remove the second material to form the plurality of nanosheets comprising the cladding material (converts the whole cladding layer into silicon germanium alloy, ¶ [0032]).
Artisans in art would have appreciated applying cladding and annealing processes to the active channels can improve lattice structures, reduce dislocation density, and improve crystallinity. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add the cladding and annealing steps as taught by Hsu to the fabrication method of Cheng-Ando to improve the lattice crystallinity of the transistors.
Regarding claim 7, Cheng in view of Ando and Hsu discloses the method of claim 6. Hsu discloses the second material comprises silicon (Hsu: ¶ [0022]).
Regarding claim 8, Cheng in view of Ando and Hsu discloses the method of claim 6. Hsu discloses wherein the cladding material comprises silicon germanium (Hsu: ¶ [0034]).
Regarding claim 11, Cheng in view of Ando and Hsu discloses the method of claim 6. Hsu discloses wherein a temperature of the annealing is in the range of from about 600 ºC to about 1100 ºC (Hsu: ¶ [0032]).
Regarding claim 18, Ching in view of Ando discloses the method of claim 13. Cheng further discloses wherein forming the plurality of nanosheets from the superlattice structure comprises: selectively etching the superlattice structure to form the plurality of nanosheets and the corresponding plurality of voids (Fig. 5, ¶ [0057]), the plurality of nanosheets comprising the second material, the second material comprising silicon ¶ [0046]);
Ching is silent regarding depositing a cladding material around each of the plurality of nanosheets, the cladding material comprising silicon germanium; dry oxidizing the plurality of nanosheets to form a plurality of oxide layers surrounding the cladding material; and annealing the plurality of nanosheets to remove the second material to form the plurality of nanosheets comprising the cladding material, wherein a temperature of the annealing is in a range of from about 600 ºC to about 1100 ºC.
Hsu, in the same field of endeavor, discloses a superlattice (nanosheet device, ¶ [0003]) forming nanosheet channels (215, Fig. 2B) and voids (277, Fig. 2B) wherein cladding (116) deposited on the channel layer (215) (operation 104, ¶ [0028]); dry oxidizing (thermal drive-in to drive oxide into the channel by reacting with oxygen, operation 106, ¶ [0034]) the plurality of nanosheets to form a plurality of oxide layers surrounding the cladding material (280, ¶ [0034]); and annealing (thermal drive-in to move elements in cladding 216 into the channel 215, operation 107, ¶ [0032]) the plurality of nanosheets to remove the second material to form the plurality of nanosheets comprising the cladding material (converts the whole cladding layer into silicon germanium alloy, ¶ [0032]) wherein a temperature of the annealing is in a range of from about 600 ºC to about 1100 ºC (¶ [0032]).
Artisans in art would have appreciated applying cladding and annealing processes to the active channels can improve lattice structures, reduce dislocation density, and improve crystallinity. As such, it would have been obvious to one of ordinary skill in the art before the active filing date of the invention to add the cladding and annealing steps as taught by Hsu to the fabrication method of Cheng-Ando to improve the lattice crystallinity of the transistors.
Claim(s) 9, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable by Cheng (US 20200266060 A1) in view of Ando (US 10236217 B1), Hsu (US 20220093472 A1) and Colombeau (US 20200152493 A1)
Regarding claim 9, Cheng in view of Ando and Hsu discloses the method of claim 6. Cheng, Ando, and Hsu are silent regarding wherein forming the plurality of nanosheets further comprises trimming the plurality of nanosheets before depositing the cladding material.
Colombeau, an analogous art, discloses (¶ [0070]) a superlattice structure (Fig. 6) forming nanosheet channels (8) and voids (Fig. 10A) wherein cladding material (24, Fig. 12A) deposited on trimmed channels (8’, Fig. 12A).
Artisans in the art would have appreciated applying cladding material on a trimmed channels would allow for the cladding material to conform to the desired channel shape, avoiding defects or misalignment of the cladding material. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to employ the trimming step of Colombeau to the method of Cheng-Ando-Hsu to allow for the control of the deposition of the cladding layer over the nanosheet channels.
Regarding claim 19, Cheng in view of Ando and Hsu discloses the method of claim 18. Cheng, Ando and Hsu are silent regarding wherein forming the plurality of nanosheets further comprises trimming the plurality of nanosheets before depositing the cladding material.
Colombeau, an analogous art, discloses (¶ [0070]) a superlattice structure (Fig. 6) forming nanosheet channels (8) and voids (Fig. 10A) wherein cladding material (24, Fig. 12A) deposited on trimmed channels (8’, Fig. 12A).
Artisans in the art would have appreciated applying cladding material on a trimmed channels would allow for the cladding material to conform to the desired channel shape, avoiding defects or misalignment of the cladding material. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to employ the trimming step of Colombeau to the method of Cheng-Ando-Hsu to allow for the control of the deposition of the cladding layer over the nanosheet channels.
Claim(s) 10, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable by Cheng (US 20200266060 A1) in view of Ando (US 10236217 B1), Hsu (US 20220093472 A1) and Jacob (US 20150255295 A1)
Regarding claim 10, Cheng in view of Ando and Hsu discloses the method of claim 6. Cheng is silent regarding wherein forming the plurality of nanosheets further comprises forming a dielectric cap before the annealing and removing the dielectric cap after the annealing.
Jacob discloses (Fig. 3B, ¶¶ [0018, 0038]) forming a protection layer (118) on a fin structure prior to performing an oxidation thermal anneal process and removing the protection layer afterwards. While Jacob does not disclose forming a protection layer on nanosheet channels, artisans in the art would have appreciated the necessity of forming a protection layer on sidewalls of nanosheet channels prior to annealing process and removing it afterwards would protect the semiconductor device from the heat damage and undesired diffusion of atoms. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a dielectric layer prior to the annealing process to stabilize the channel layer from heat damage and prevent diffusion of atoms into the channel as taught by Jacob to the method of Cheng. Doing so would result in channel stabilization and protection during high-temperature processing.
Regarding claim 20, Cheng in view of Ando and Hsu discloses the method of claim 18. Cheng is silent regarding wherein forming the plurality of nanosheets further comprises forming a dielectric cap before the annealing and removing the dielectric cap after the annealing.
Jacob discloses (Fig. 3B, ¶¶ [0018, 0038]) forming a protection layer (118) on a fin structure prior to performing an oxidation thermal anneal process and removing the protection layer afterwards. While Jacob does not disclose forming a protection layer on nanosheet channels, artisans in the art would have appreciated the necessity of forming a protection layer on sidewalls of nanosheet channels prior to annealing process and removing it afterwards would protect the semiconductor device from the heat damage and undesired diffusion of atoms. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a dielectric layer prior to the annealing process to stabilize the channel layer from heat damage and prevent diffusion of atoms into the channel as taught by Jacob to the method of Cheng. Doing so would result in channel stabilization and protection during high-temperature processing.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu (US 10797163 B1) and Chang (US 20210202709 A1) disclose a superlattice structure forming nanochannels and voids.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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