DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (Fig. 10) (claims 1-20) in the reply filed on 08/13/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Piao et al (CN 111882985 A).
Regarding claim 1: Piao teaches in Fig. 1-6B about a display device comprising:
PNG
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474
722
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Greyscale
PNG
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420
716
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Greyscale
a substrate (comprising, 110, 120, 130);
a first display layer 200 on a first surface of the substrate (Fig. 1);
a second display layer 300 on a second surface of the substrate (Fig. 2);
a first pixel P1/P2 of the first display layer (Fig. 3A); and
a second pixel P3 of the second display layer (Fig. 4A), wherein the first pixel and the second pixel comprise different numbers of transistors (page 9 teaches the third pixel circuit may include a different number of thin film transistors and a different number of storage capacitors with the first pixel circuit and the second pixel circuit).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 14-20 are rejected under 35 U.S.C. 103 as being obvious over Piao et al (CN 111882985 A) in view of Jin et al (CN 113823660 A) and Lee et al. (US PGPUB 2021/0399080 A)
Regarding claim 2: Piao teaches wherein a second pixel circuit of the second pixel comprises a different number of transistors than a first pixel circuit of the first pixel except larger number of transistors.
Jin teaches in page 13 the number of thin film transistors included in the first pixel circuit unit PC1 may be less than or equal to the number of thin film transistors included in the second pixel circuit unit PC2.
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the application was filed, to have the feature as claimed as the number of thin-film transistors and the number of storage capacitors included in the pixel circuit PC may be variously changed according to the design of the pixel circuit PC (Lee, [0063]).
Regarding claim 14: Piao teaches in Fig. 3A, 4A wherein the first display layer and the second display layer have different areas.
Regarding claim 15: Piao teaches in Fig. 3A, 4A wherein the first display layer has a larger area than that of the second display layer.
Regarding claim 16: Jin teaches in page 8 further comprising a driving circuit on the second surface and connected to the first display layer and the second display layer.
Regarding claim 17: Jin teaches in page 9 wherein the driving circuit is connected to the first display layer through a first pad terminal of the driving circuit, and the driving circuit is connected to the second display layer through a second pad terminal of the driving circuit.
Regarding claim 18: Jin teaches in page 9 wherein the first pad terminal is connected to the first display layer through a first pad on the second surface, and the second pad terminal is connected to the second display layer through a second pad on the second surface.
Regarding claim 19: Jin teaches wherein the driving circuit supplies a gate signal, a data signal, and an emission signal to the first display layer through the first pad terminal, and the driving circuit supplies a gate signal, a data signal, and an emission signal to the second display layer through the second pad terminal (page 9 teaches about data lines, DL, gate lines GL, emission lines EL which would provide the respective signals).
Regarding claim 20: Piao teaches wherein the first pixel further comprises a first light emitting element (OLED1/OLED2) connected to the first pixel circuit, and the second pixel further comprises a second light emitting element OLED3 connected to the second pixel circuit.
Claims 3 are rejected under 35 U.S.C. 103 as being obvious over Piao et al (CN 111882985 A) in view of Jin et al (CN 113823660 A) and Lee et al. (US PGPUB 2021/0399080 A) and further in view of Yu et al. (US 10192938 B2)
Regarding claim 3: Piao in view of Jin, Lee does not explicitly teaches wherein the first pixel circuit comprises five transistors, and the second pixel circuit comprises eight transistors.
However Piao teaches in page 9 the number of transistors can be different in different pixel circuits and Jin teaches in page 13 the number of transistors can be two, three, seven transistos and Lee teaches [0063] the number of transistors can be varied according to the design of the pixel circuit PC. Yu further teaches in Fig. 3 pixel circuit 22 has seven transistors T1, T2, T3, T4, T5, T6, and TD and one capacitor Cst, so pixel circuit 22 may sometimes be referred to as a 7T1C pixel circuit. Other numbers of transistors and capacitors may be used in pixels 22 if desired (e.g., fewer transistors, more transistors, more capacitors, etc.)
Thus, it would have been obvious to one of the ordinary skill in the art at the time the application was filed to have the number of transistors as claimed in different pixel circuits with routine experiment and optimization since number of transistors varies according to the design of the pixel circuit PC, Lee ([0063]). In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “a first transistor comprising a gate electrode connected to a first node, and connected between a second node and a third node;
a second transistor comprising a gate electrode connected to a first gate line, and connected between a data line and the first node;
a third transistor comprising a gate electrode connected to a third gate line, and connected between a reference voltage line and the first node;
a fourth transistor comprising a gate electrode connected to a second gate line, and connected between a third node and an initialization voltage line; and
a fifth transistor comprising a gate electrode connected to an emission line, and connected between a driving voltage line and the second node” in combination with other limitations as a whole.
Claims 5-8 are also allowable being dependent on allowable claim 4.
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “a first transistor comprising a gate electrode connected to a third node, and connected between a first node and a second node; a second transistor comprising a gate electrode connected to a first gate line, and connected between a data line and the first node; a third transistor comprising a gate electrode connected to a second gate line, and connected between the third node and the second node; a fourth transistor comprising a gate electrode connected to a third gate line, and connected between the third node and a first initialization voltage line; a fifth transistor comprising a gate electrode connected to an emission line, and connected between a driving voltage line and the first node; a sixth transistor comprising a gate electrode connected to the emission line, and connected between the second node and a fourth node; a seventh transistor comprising a gate electrode connected to a fourth gate line, and connected between the fourth node and a second initialization voltage line; and an eighth transistor comprising a gate electrode connected to the fourth gate line, and connected between a bias voltage line and the first node” in combination with other limitations as a whole.
Claims 10-13 are also allowable being dependent on allowable claim 9.
Conclusion
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
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