Acknowledgment
The amendment filed on September 2, 2026 responding to the Office Action mailed on June 3, 202 has been entered. This Office Action fully considers the amendments to the pending application in which claims 1 to 10 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 9-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. 2023/0402340 (Lin).
Regarding claim 1 and referring to annotated Figures 1, 3 and 10-11, Lin
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discloses a method for fabricating semiconductor device, comprising:
providing a first wafer, 110 [0019], and a second wafer, 156 [0043]; and
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bonding the first wafer onto a carrier, C [0018], by forming an adhesive layer, AD [0018], between the carrier and the first wafer, as shown, and
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conducting a first end of line (FEOL) process, e.g. PECVD or CVD deposition of dielectric 140 [0027], on the first wafer, as shown, after bonding the first wafer onto the carrier, as shown and described. Examiner notes the overlap of FEOL and BEOL processes. Examiner notes that merely inspecting or counting the wafer would meet the claim, i.e. there is a vast and trivial universe of species that satisfy FEOL and BEOL steps.
Regarding claim 2 which depends upon claim 1, further comprising: conducting the front end of
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line (FEOL) process and a back end of line (BEOL) process, e.g. formation of bond pads 116 or 156b, or vias 114 or on the first wafer and the second wafer; forming direct bond interconnects (DBI), 154 [0034], on the first wafer and the second wafer, as shown; bonding the first wafer and the second wafer, as shown and described [0042]; and performing a de-bonding process to detach the carrier and the first wafer, as shown in Figure 11. Note: The claim does not required the first and second wafer to be bonded directly to each other.
Regarding claim 3 which depends upon claim 2, Lin teaches performing a hybrid bonding process to bond the first wafer and the second wafer, i.e., the pads are embedded in dielectric and there is no solder between the pads [0043].
Regarding claims 9, Lin teaches at [0018] the carrier may be glass or silicon while at [0019] the first wafer may be silicon and so teaches the carrier and the first wafer comprise (a) same material.
Regarding claim 10 Lin teaches at [0018] the carrier may be glass or silicon while at [0019] the first wafer may be silicon and so teaches the carrier and the first wafer comprise different materials.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Lin.
Regarding claim 4 which depends upon claim 3, Lin teaches that 156 may be include circuits, active device and passive devices and conductors 158b are embedded in dielectric to form bonding structure 158 [0042]. Examiner understands Lin to suggest that the bonding structure 158 is on the finished wafer and so Lin teaches and suggests that the method comprises reversing the second wafer by facing a front side of the second wafer to a front side of the first wafer; and bonding the DBI on the second wafer to the DBI on the first wafer where again the claim does not require direct contact of the first and second wafer bonding structures.
Regarding claim 5 which depends upon claim 2, and referring to the discussion above, Examiner takes that position that Lin suggests forming the DBI on front sides of the first wafer and the second wafer, i.e. bonding front-to-front manner.
Claims 1-5, 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 2025/0279397 (Chung) and Lin.
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Regarding claim 1 Chung discloses at annotated Figure 3G a method for fabricating semiconductor device, comprising:
providing a first wafer, e.g. 112/10 [0059-62], and a second wafer, 122/20 [0059-61]; and
bonding the first wafer, 112/10, onto a carrier, CR1 [0060], by forming an adhesive layer, not shown but described at [0060], between the carrier and the first wafer, as annotated.
Chung does not explicitly teach conducting a front end of line (FEOL) process on the first wafer after bonding the first wafer to the carrier.
Referring to the discussion above, Lin teaches a suitable modification of Lin’s method includes conducting a front end of line (FEOL) process on the first wafer after bonding the first wafer to the carrier.
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Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the method of claim 1 comprising conducting a front end of line (FEOL) process on the first wafer after bonding the first wafer to the carrier because Lin teaches this is a useful modification of Lin’s method and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
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Regarding claim 2 which depends upon claim 1, Chung teaches and suggests at [0078] and Figures 7A and 7B, conducting a front end of line (FEOL) process and a back end of line (BEOL) process on the first wafer, 112, where 116 is a via middle structure, [0060], formed after the FEOL process but before the BEOL process, and also suggest the second wafer, 122 where 126 is also a via middle structure; forming direct bond interconnects (DBI), 142a/142b [0045], on the first wafer and the second wafer, as shown in Figure 3G; bonding the first wafer and the second wafer, as shown; and performing a de-bonding process to detach the carrier and the first wafer, as shown in Figure 3I and described at [0067].
Regarding claim 3 which depends upon claim 2, Chung teaches performing a hybrid bonding process to bond the first wafer and the second wafer at [0045].
Regarding claim 4 which depends upon claim 3, Chung teaches an alternative embodiment of his method at Figures 7A and 7B wherein the hybrid bonding process comprises: reversing the second wafer by facing a front side of the second wafer to a front side of the first wafer; and bonding the DBI on the second wafer to the DBI on the first wafer at [0079].
Regarding claim 5 which depends upon claim 2, Chung teaches an alternative embodiment of his method at Figures 7A and 7B comprising forming the DBI on front sides of the first wafer and the second wafer, i.e. bonding front-to-front manner [0079].
Regarding claim 7 which depends upon claim 1, at [0060] Chung teaches thinning the first wafer, 112; and bonding the first wafer to the carrier, CR1, as shown.
Regarding claim 10 which depends upon claim 1, Chung teaches the carrier may be glass at [0060] and the first wafer, 112 may comprise silicon [0036] and so teaches the carrier and first wafer comprise different materials.
Allowable Subject Matter
Claims 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6 the prior art does not teach the method of claim 2, further comprising: forming metal interconnections on a backside of the first wafer; and performing a chip probing test on the metal interconnections.
Regarding claim 8 the prior art does not teach the method of claim 1, wherein a thickness of the first wafer is less than a thickness of the second wafer.
Response to Arguments
Applicant’s arguments with respect to claim 1 has been considered but are moot because the new ground of rejection does not rely on the Cheng reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893
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