Prosecution Insights
Last updated: July 17, 2026
Application No. 18/660,207

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
May 09, 2024
Priority
Mar 29, 2024 — TW 113111909
Examiner
SCHOENHOLTZ, JOSEPH
Art Unit
Tech Center
Assignee
United Microelectronics Corp.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1197 granted / 1312 resolved
+31.2% vs TC avg
Minimal -5% lift
Without
With
+-4.9%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
11 currently pending
Career history
1325
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
74.3%
+34.3% vs TC avg
§102
5.0%
-35.0% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1312 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office Action is in response to Applicant’s application 18/660,207 filed on May 9, 2024 in which claims 1 to 10 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings submitted on May 9, 2024 have been reviewed and accepted by the Examiner. Information Disclosure Statement The Information Disclosure Statement (IDS), filed on May 9, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner. Priority Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. PNG media_image1.png 684 708 media_image1.png Greyscale Claims 1, 7 and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. 2025/0279397 (Chung). Regarding claim 1 Chung discloses at annotated Figure 3C-3C a method for fabricating semiconductor device, comprising: providing a first wafer, e.g. 112/10 [0059-62, and a second wafer, 122/20 [0059-61]; and bonding the first wafer, 112/10, onto a carrier, CR1 [0060], by forming an adhesive layer, not shown but described at [0060], between the carrier and the first wafer, as annotated. Regarding claim 7 which depends upon claim 1, at [0060] Chung teaches thinning the first wafer, 112; and bonding the first wafer to the carrier, CR1, as shown. Regarding claim 10 which depends upon claim 1, Chung teaches the carrier may be glass at [0060] and the first wafer, 112 may comprise silicon [0036] and so teaches the carrier and first wafer comprise different materials. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chung. PNG media_image2.png 756 690 media_image2.png Greyscale PNG media_image3.png 630 680 media_image3.png Greyscale Regarding claim 2 which depends upon claim 1, Chung teaches and suggests at [0078] and Figures 7A and 7B, conducting a front end of line (FEOL) process and a back end of line (BEOL) process on the first wafer, 112, where 116 is a via middle structure, [0060], formed after the FEOL process but before the BEOL process, and also suggest the second wafer, 122 where 126 is also a via middle structure; forming direct bond interconnects (DBI), 142a/142b [0045], on the first wafer and the second wafer, as shown in Figure 3G; bonding the first wafer and the second wafer, as shown; and performing a de-bonding process to detach the carrier and the first wafer, as shown in Figure 3I and described at [0067]. Regarding claim 3 which depends upon claim 2, Chung teaches performing a hybrid bonding process to bond the first wafer and the second wafer at [0045]. Regarding claim 4 which depends upon claim 3, Chung teaches an alternative embodiment of his method at Figures 7A and 7B wherein the hybrid bonding process comprises: reversing the second wafer by facing a front side of the second wafer to a front side of the first wafer; and bonding the DBI on the second wafer to the DBI on the first wafer at [0079]. Regarding claim 5 which depends upon claim 2, Chung teaches an alternative embodiment of his method at Figures 7A and 7B comprising forming the DBI on front sides of the first wafer and the second wafer, i.e. bonding front-to-front manner [0079]. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chung and U.S. 2025/0029949 (Sung). Regarding claim 9 which depends upon claim 1, Chung does not explicitly teach the carrier and the first wafer comprise same material. Sung is directed to wafer-to-wafer assembly methods. At [0018], Sung teaches that a carrier, 100, for a bonding process may be glass substrate or a silicon substrate. Taken as a whole, the prior art is directed to wafer bonding methods. Sung teaches that a silicon substrate may be substituted for a glass substrate. Accordingly, it would have been obvious to a person of ordinary skill in the art to substitute Chung’s glass carrier a silicon carrier, as taught by Sung, resulting in the carrier and the first wafer comprise same material, i.e., silicon, because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Allowable Subject Matter Claims 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 6 the prior art does not teach the method of claim 2, further comprising: forming metal interconnections on a backside of the first wafer; and performing a chip probing test on the metal interconnections. Regarding claim 8 the prior art does not teach the method of claim 1, wherein a thickness of the first wafer is less than a thickness of the second wafer. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.E. Schoenholtz/Primary Examiner, Art Unit 2893
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Prosecution Timeline

May 09, 2024
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
86%
With Interview (-4.9%)
1y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1312 resolved cases by this examiner. Grant probability derived from career allowance rate.

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