DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-12) in the reply filed on 6.23.2026 is acknowledged.
Claims 1-13 and 20 are elected since claims 1, 4, 13 and 20 are linking claims.
Claims 14-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6.23.2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5.9.2024 is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12-13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng et al. (US 5858870 A) in view of Wang et al. (US 6291331 B1).
Regarding claim 1, Zheng discloses (Fig. 7) a semiconductor device, comprising:
a semiconductor substrate (10);
pad structures (20) disposed on the semiconductor substrate;
a filling dielectric layer (32+36) disposed on the semiconductor substrate, wherein the filling dielectric layer covers the pad structures, and the filling dielectric layer comprises:
a first portion (36) disposed between the pad structures in a horizontal direction; and
a second portion (32) disposed above the pad structures in a vertical direction;
a first
a second second compressive stress layer (40) is greater than a (total) thickness of the second portion (32) of the filling dielectric layer (Fig. 7)
Zheng fails to disclose a first compressive stress layer and a second compressive stress layer disposed on the first compressive stress layer.
Wang discloses (Fig. 3) a first compressive stress layer (88, “layer 88 is the layer of compressive PECVD”) and a second compressive stress layer (92, “layer 92 is the layer of compressive PECVD”) disposed on the first compressive stress layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify layers 38 and 40 of Zheng to be compressive stress layers in view of Wang so as to prevent cracks in metallization stacks (Wang, Title).
Regarding claim 2, Zheng/Wang (in combination) discloses the semiconductor device according to claim 1, wherein a compressive stress of the first compressive stress layer (Wang: 88, “layer 88 is the layer of compressive PECVD”) is greater than a compressive stress (of 32 and/or 36) of the filling dielectric layer (Zheng: 32+36, no stress disclosed and the claim is inherently met).
In the event the claim is not inherently met, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed relationship so as to prevent cracks in metallization stacks (Wang, Title) while preventing the overexertion of compressive stress by modulating compressive stresses across the device.
Regarding claim 3, Zheng/Wang (in combination) the semiconductor device according to claim 1, wherein a compressive stress of the second compressive stress layer (Wang: 92, “layer 92 is the layer of compressive PECVD”) is greater than a compressive stress (of 32 and/or 36) of the filling dielectric layer (Zheng: 32+36, no stress disclosed and the claim is inherently met).
In the event the claim is not inherently met, which the examiner does not concede, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed relationship so as to prevent cracks in metallization stacks (Wang, Title) while preventing the overexertion of compressive stress by modulating compressive stresses across the device.
Regarding claim 4, Zheng/Wang fails to disclose the semiconductor device according to claim 1, wherein a compressive stress of the second compressive stress layer is greater than a compressive stress of the first compressive stress layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed relationship so as to prevent cracks in metallization stacks (Wang, Title) while preventing the overexertion of compressive stress by modulating compressive stresses across the device.
Regarding claim 5, Zheng/Wang discloses the semiconductor device according to claim 1, wherein the thickness of the second compressive stress layer (40) is greater than a thickness of the first compressive stress layer (38, Fig. 7).
Regarding claim 6, Zheng/Wang discloses the semiconductor device according to claim 1, wherein a thickness of the first portion (36) of the filling dielectric layer is greater than the thickness of the second portion (32) of the filling dielectric layer (Fig. 7).
Regarding claim 7, Zheng/Wang fails to disclose the semiconductor device according to claim 1, wherein a thickness of the first portion (36) of the filling dielectric layer is greater than the thickness of the second compressive stress layer (40).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed relationship so as to minimize the size of the device above the pad structures and/or because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Regarding claim 8, Zheng/Wang fails to disclose the semiconductor device according to claim 1, wherein a thickness of the first portion (36) of the filling dielectric layer is greater than a sum of the thickness of the second compressive stress layer (40) and a thickness of the first compressive stress layer (38).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed relationship so as to minimize the size of the device above the pad structures and/or because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Regarding claim 9, Zheng/Wang discloses the semiconductor device according to claim 1, wherein a material composition of the first compressive stress layer is identical to a material composition of the second compressive stress layer (“layer 88 is the layer of compressive PECVD” and “layer 92 is the layer of compressive PECVD”).
Regarding claim 10, Zheng/Wang discloses the semiconductor device according to claim 1, wherein a top (not topmost) surface of the first portion (36) of the filling dielectric layer is lower than the top(most) surface of the second portion (32) of the filling dielectric layer in the vertical direction (Fig. 7).
Regarding claim 12, Zheng/Wang fails to disclose the semiconductor device according to claim 1, wherein the semiconductor substrate comprises an interconnection structure, and each of the pad structures is electrically connected with the interconnection structure.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to provide an interconnection structure as claimed so as to enable electrical addressing of active devices in or over the semiconductor substrate.
Regarding claim 13, Zheng discloses (Fig. 7) A manufacturing method of a semiconductor device, comprising:
providing a semiconductor substrate (10);
forming pad structures (20) on the semiconductor substrate;
forming a filling dielectric layer (32+36) and a first
a first portion (36) disposed between the pad structures in a horizontal direction; and
a second portion (32) disposed above the pad structures in a vertical direction, wherein the first
forming a second
Zheng fails to disclose a first compressive stress layer and a second compressive stress layer disposed on the first compressive stress layer.
Wang discloses (Fig. 3) a first compressive stress layer (88, “layer 88 is the layer of compressive PECVD”) and a second compressive stress layer (92, “layer 92 is the layer of compressive PECVD”) disposed on the first compressive stress layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify layers 38 and 40 of Zheng to be compressive stress layers in view of Wang so as to prevent cracks in metallization stacks (Wang, Title).
Regarding claim 20, Wang/Zheng fails to disclose the manufacturing method of the semiconductor device according to claim 13, wherein a compressive stress of the second compressive stress layer (40) is greater than a compressive stress of the first compressive stress layer (38).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to arrive at the claimed relationship so as to prevent cracks in metallization stacks (Wang, Title) while preventing the overexertion of compressive stress by modulating compressive stresses across the device.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to disclose or suggest the first compressive stress layer directly contacts the first portion and the second portion of the filling dielectric layer as recited within the context of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20080124940 A1 to Yu et al. discloses dielectric layers (105, 106) in between pad structures (102, Fig. 1D).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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/Andres Munoz/ Primary Examiner, Art Unit 2818
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