DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 18/19/2026 has been accepted and entered. Claims 1-20 remain pending in this application. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed on 06/02/2026.
Claim Objections
Claims 8-15 is/are objected to because of the following informalities:
Claim 8 recites “in a plan view” in Line L20 but should read –in the plan view --.
The balance of claims are objected to for being dependent upon an already objected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8-11, 13, 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. (US20230073072A1 from IDS-Hong72).
Regarding claim 8, Hong72 discloses a display panel (Title) comprising:
a substrate (Substrate 100-Examiner's annotated Fig 4B) comprising
a first display area (First display area DA1-Examiner's annotated Fig 4B) in which first display elements are located (First display elements LED located in first display area DA1 -Examiner's annotated Fig 4B) and
a second display area (Second display area DA2 including a transmission area TA-Examiner's annotated Fig 4B) in which second display elements (Second display elements LED located in second display area DA2-examiner's annotated Fig 4B)and a transmission area (Second display area DA2 including a transmission area TA-Examiner's annotated Fig 4B) are located;
a pixel circuit layer located on the substrate (Pixel Circuit PC located on substrate 100-Examiner's annotated Fig 11B) and including
first pixel circuits located in the first display area (First Pixel Circuit PC located in first display area DA1, connected to first display element OLED1-Examiner's annotated Fig 15) and
connected to the first display elements (First Pixel Circuit PC located in first display area DA1, connected to first display element OLED1-Examiner's annotated Fig 15) and
second pixel circuits located in the second display area (Second Pixel Circuit PC located in second display area DA2, connected to second display element OLED2-Examiner's annotated Fig 15) and
connected to the second display elements (Second Pixel Circuit PC located in second display area DA2, connected to second display element OLED2-Examiner's annotated Fig 15);
a bottom metal layer located between the substrate and the pixel circuit layer (Bottom metal layer BML located between pixel circuit layer PC and substrate 100, at least partially overlapping pixel circuit layer PC-Examiner's annotated Fig 15) and
at least partially overlapping the pixel circuit layer (Bottom metal layer BML located between pixel circuit layer PC and substrate 100, at least partially overlapping pixel circuit layer PC-Examiner's annotated Fig 15);
a thin-film encapsulation layer covering the first display elements and the second display elements (Thin-film encapsulation layer 300 covering OLED1 and OLED2-Examiner's annotated Fig 15); and
an input sensing layer located on the thin-film encapsulation layer (Input sensing layer 400 located on thin-film encapsulation layer 300-Examiner's annotated Fig 15),
wherein the first display elements and the second display elements include a counter electrode (First display elements OLED1 and second display elements OLED2 including Counter-electrode 230-Examiner's annotated Fig 15),
the counter electrode including at least one transmission hole located in an area corresponding to the transmission area (First display elements OLED1 and second display elements OLED2 including Counter-electrode 230, including transmission hole 230OP corresponding to the transmission area TA-Examiner's annotated Fig 15), and
wherein at least one of a first metal layer located on a same layer as the bottom metal layer (First metal on same layer as Bottom metal layer BML located between pixel circuit layer PC and substrate 100, at least partially overlapping an edge of the transmission hole TA in (z, ob) plan view-Examiner's annotated Fig 11B),
a second metal layer included in the pixel circuit layer (Second metal CE2 being on the same layer as electrode SE of the thin-film transistor TFT in the second pixel circuit-Updated Examiner’s annotated Fig 11B), and
a third metal layer included in the input sensing layer (Input sensing layer 400 including a first touch conductive layer with third metal layer ML2, first touch insulating layer 403, second touch conductive layer with metal layer ML1, and second touch insulating layer 405 sequentially stacked-Examiner's annotated Fig 10)
at least partially overlaps an edge of the at least one transmission hole in a plan view (First/Right metal being a portion of Bottom metal layer BML so on the same layer, including an opening BML-OP so provided in a closed shape overlapping the entire edge of the transmission hole 230OP as indicated by the dashed line rectangle, comprising opening BML-OP exposing the central portion of transmission hole 230OP-Updated Examiner’s annotated Fig 11B),
wherein the first metal layer, the second metal layer or the third metal layer is spaced apart from the bottom metal layer in a plan view (First, second, third metal layers spaced apart from the bottom metal layer BML in a plan view-Updated Examiner's annotated Fig 11B).
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Regarding claim 9, Hong72 discloses all the elements of claim 8, as noted above.
Hong72 further discloses a display panel comprising:
wherein the first metal layer is provided in a closed shape overlapping the entire edge of the at least one transmission hole (First metal being a portion of Bottom metal layer BML so on the same layer, including an opening BML-OP so provided in a closed shape overlapping the entire edge of the transmission hole 230OP as indicated by the dashed line rectangle-Examiner's annotated Fig 11B) and
comprising an opening through which a central portion of the at least one transmission hole is exposed (First metal being a portion of Bottom metal layer BML so on the same layer, including an opening BML-OP so provided in a closed shape overlapping the entire edge of the transmission hole 230OP as indicated by the dashed line rectangle, comprising opening BML-OP exposing the central portion of transmission hole 230OP-Examiner's annotated Fig 11B).
Regarding claim 10, Hong72 discloses all the elements of claim 8, as noted above.
Hong72 further discloses a display panel comprising:
wherein the second metal layer is located on a same layer as one electrode of a thin-film transistor included in the second pixel circuits (Second metal layer comprising CE2 being on the same layer as electrode SE of the thin-film transistor TFT in the second pixel circuit-Examiner's annotated Fig 10).
Regarding claim 11, Hong72 discloses all the elements of claim 8, as noted above.
Hong72 further discloses a display panel comprising:
wherein the input sensing layer has a structure in which a first touch conductive layer, a first touch insulating layer, a second touch conductive layer, and a second touch insulating layer are sequentially stacked (Input sensing layer 400 including a first touch conductive layer with third metal layer ML2, first touch insulating layer 403, second touch conductive layer with metal layer ML1, and second touch insulating layer 405 sequentially stacked-Examiner's annotated Fig 10, [0149]), and
wherein the third metal layer is located on a same layer as the first touch conductive layer or the second touch conductive layer (third metal layer ML2 being part of first touch conductive layer ML2 so on the same layer-Annotated Fig 2).
Regarding claim 13, Hong72 discloses all the elements of claim 8, as noted above.
Hong72 further discloses a display panel comprising:
wherein a pixel-defining film defining emission areas of the first display elements and the second display elements comprises an opening located in an area corresponding to the transmission area (Pixel defining film 610 defining emission areas 610OP2 of first display elements OLED1 and second display elements OLED2, comprising opening 610-OP3 overlapping an edge of the transmission area TA-Examiner's annotated Fig 11B).
Regarding claim 15, Hong72 discloses all the elements of claim 8, as noted above.
Hong72 further discloses a display panel comprising:
wherein the transmission area comprises
a first transmission area corresponding to a body portion of the counter electrode (First transmission area on the edge of second transmission area indicated by the dashed line rectangle-Examiner's annotated Fig 11A) and
a second transmission area corresponding to the at least one transmission hole of the counter electrode (Second transmission area indicated by the dashed line rectangle corresponding to transmission hole of counter electrode 230-OP-Examiner's annotated Fig 11A), and
wherein a light transmittance of the second transmission area is higher than a light transmittance of the first transmission area (Optical functional layer OFL being a polarizing film so having a light transmittance, being on layer 400, having an opening OFL-OP corresponding to transmission area TA where the light transmittance being improved so the light transmittance of the second transmission area corresponding to OFL-OP being higher than the light transmittance of the first transmission area outside OFL-OP-[0081], [0082]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US20200373372A1 from IDS-Chung72) in view of Lee et al. (US 20230103050 A1-Lee50).
Regarding claim 1, Chung72 discloses a display panel (Title) comprising:
a substrate (Substrate 100-Examiner's annotated Fig 5B) comprising
a first display area (First display area DA-Examiner's annotated Fig 5B) and
a second display area (Second display area SA including a transmission area TA-Examiner's annotated Fig 5B),
the second display area including a transmission area (Second display area SA including a transmission area TA-Examiner's annotated Fig 5B);
first display elements located in the first display area (First/Left display elements OLED located in first display area DA -Examiner's annotated Fig 5B) and
second display elements located in the second display area (Second/Right display elements OLED located in second display area SA-examiner's annotated Fig 5B),
the first display elements and the second display elements including
a counter electrode integrally provided over the first display area and the second display area (Counter-electrode 230 integrally provided over first display area DA and second display area SA-Examiner's annotated Fig 9) and including
at least one transmission hole located in an area corresponding to the transmission area (Counter-electrode 230 integrally provided over first display area DA and second display area SA, including transmission hole 230OP corresponding to the transmission area TA-Examiner's annotated Fig 9); and
a blocking layer at least partially overlapping an edge of the at least one transmission hole (Blocking layer 400 overlapping an edge of the transmission hole 230OP- Examiner's annotated Fig 9, Fig 11).
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Chung72 does not disclose a display panel
wherein the transmission area includes
a first transmission area overlapping the counter electrode and
a second transmission area overlapping the at least one transmission hole of the counter electrode in a plan view, and
each of the first transmission area and the second transmission area is exposed by the blocking layer.
Lee50 teaches a display panel (Display panel 10-Fig 4, [0058] L1-3)
wherein the transmission area (Transmission area TA indicated by the dashed line rectangle-Examiner’s annotated Fig 4) includes
a first transmission area overlapping the counter electrode (First Transmission Area overlapping counter electrode 230, as indicated by the dashed and solid line rectangular area-Examiner's annotated Fig 4) and
a second transmission area overlapping the at least one transmission hole of the counter electrode in a plan view (Second Transmission Area not overlapping counter electrode 230, as indicated by the solid line rectangular area in plan view (x,z)-Examiner's annotated Fig 4), and
each of the first transmission area and the second transmission area is exposed by the blocking layer (Blocking layer BML exposing both first and second transmission areas-Examiner's annotated Fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display apparatus of Chung72, as taught by Lee50 for the purpose of
reducing the image distortion (for example, flare, haze, etc.) (Lee50: [0069]).
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Regarding claim 2, Chung72 and Lee50 combination discloses all the elements of claim 1, as noted above.
Chung72 further discloses a display panel comprising:
a pixel circuit layer located on the substrate (Pixel Circuit PC located on substrate 100-Examiner's annotated Fig 9) and including
first pixel circuits respectively connected to the first display elements (Abstract L5-8) and
second pixel circuits respectively connected to the second display elements (Abstract L5-8); and
a bottom metal layer located between the substrate and the pixel circuit layer (Bottom metal layer 400 between pixel circuit PC and substrate 100-Examiner's annotated Fig 9) and
overlapping at least one thin-film transistor included in the second pixel circuits (Bottom metal layer 400 between pixel circuit PC and substrate 100 overlapping on thin-film transistor included in the second pixel circuit-Examiner's annotated Fig 9),
wherein the blocking layer and the bottom metal layer are formed of a same material and
are located on a same layer (Bottom metal layer 400, and blocking metal layer 400 being the same layer so on the same layer, and formed of the same material-Fig 9).
Regarding claim 3, Chung72 and Lee50 combination discloses all the elements of claim 2, as noted above.
Chung72 further discloses a display panel comprising:
wherein the blocking layer has a closed shape overlapping the entire edge of the at least one transmission hole (blocking layer 400 surrounding transmission area so having a closed shape overlapping the entire edge of at least one transmission hole 230OP-Examiner's annotated Fig 9, [0094] L13-20, Fig 6A/B, [0137]) and
includes an opening through which a central portion of the at least one transmission hole is exposed (blocking layer 400 surrounding transmission area so including an opening TA corresponding to a central portion of one transmission hole 230OP-Examiner's annotated Fig 9, [0094] L13-20).
Regarding claim 4, Chung72 and Lee50 combination discloses all the elements of claim 1, as noted above.
Chung72 further discloses a display panel comprising:
a pixel circuit layer located on the substrate (Pixel Circuit PC located on substrate 100-Examiner's annotated Fig 9) and including
first pixel circuits connected to the first display elements (Abstract L5-8) and
second pixel circuits connected to the second display elements (Abstract L5-8); and
wherein the blocking layer is a part of a wiring included in the pixel circuit layer (Blocking layer 400 connected to initialization voltage line VL or a power supply/Driving voltage ELVDD/ELVSS so being part of the pixel circuit layer-Fig 8, [0123]).
Regarding claim 5, Chung72 and Lee50 combination discloses all the elements of claim 4, as noted above.
Chung72 further discloses a display panel comprising:
wherein a portion of the wiring constituting a blocking layer has a width greater than that of another portion of the wiring (portion of wiring blocking layer 400 having a width greater than width of a pixel circuit PA, PA width being greater than PL/DL/EL/SL wiring so greater than a portion of the PL/DL/EL/SL wiring-Fig 4).
Claim(s) 1-2, 7, 16-17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Lee et al. (US 20230103050 A1-Lee50).
Regarding claim1, Hong72 discloses a display panel (Title) comprising:
a substrate (Substrate 100-Examiner's annotated Fig 4B) comprising
a first display area (First display area DA1-Examiner's annotated Fig 4B) and
a second display area (Second display area DA2 including a transmission area TA-Examiner's annotated Fig 4B),
the second display area including a transmission area (Second display area DA2 including a transmission area TA-Examiner's annotated Fig 4B);
first display elements located in the first display area (First display elements LED located in first display area DA1 -Examiner's annotated Fig 4B) and
second display elements located in the second display area (Second display elements LED located in second display area DA2-examiner's annotated Fig 4B),
the first display elements and the second display elements including
a counter electrode integrally provided over the first display area and the second display area (Counter-electrode 230 integrally provided over first display area DA1 and second display area DA2-Examiner's annotated Fig 10) and including
at least one transmission hole located in an area corresponding to the transmission area (Counter-electrode 230 integrally provided over first display area DA1 and second display area DA2, including transmission hole 230OP corresponding to the transmission area TA-Examiner's annotated Fig 11B); and
a blocking layer at least partially overlapping an edge of the at least one transmission hole (Blocking layer 610 overlapping an edge of the transmission hole 230OP-Examiner's annotated Fig 11B).
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Hong72 does not disclose a display panel
wherein the transmission area includes
a first transmission area overlapping the counter electrode and
a second transmission area overlapping the at least one transmission hole of the counter electrode in a plan view, and
each of the first transmission area and the second transmission area is exposed by the blocking layer.
Lee50 teaches a display panel (Display panel 10-Fig 4, [0058] L1-3)
wherein the transmission area (Transmission area TA indicated by the dashed line rectangle-Examiner’s annotated Fig 4) includes
a first transmission area overlapping the counter electrode (First Transmission Area overlapping counter electrode 230, as indicated by the dashed and solid line rectangular area-Examiner's annotated Fig 4) and
a second transmission area overlapping the at least one transmission hole of the counter electrode in a plan view (Second Transmission Area not overlapping counter electrode 230, as indicated by the solid line rectangular area in plan view (x,z)-Examiner's annotated Fig 4), and
each of the first transmission area and the second transmission area is exposed by the blocking layer (Blocking layer BML exposing both first and second transmission areas-Examiner's annotated Fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display apparatus of Hong72, as taught by Lee50 for the purpose of
reducing the image distortion (for example, flare, haze, etc.) (Lee50: [0069]).
Regarding claim 2, Hong72 and Lee50 combination discloses all the elements of claim 1, as noted above.
Hong72 further discloses a display panel comprising:
a pixel circuit layer located on the substrate (Pixel Circuit PC located on substrate 100-Examiner's annotated Fig 15) and including
first pixel circuits respectively connected to the first display elements (First Pixel Circuit PC located in first display area DA1, connected to first display element OLED1, on substrate 100-Examiner's annotated Fig 15) and
second pixel circuits respectively connected to the second display elements (Second Pixel Circuit PC located in second display area DA2, connected to second display element OLED2, on substrate 100-Examiner's Fig 15); and
a bottom metal layer located between the substrate and the pixel circuit layer (Bottom metal layer BML located between pixel circuit layer PC and substrate 100-Examiner's annotated Fig 15) and
overlapping at least one thin-film transistor included in the second pixel circuits (Bottom metal layer BML located between pixel circuit layer PC and substrate 100, at least partially overlapping second pixel circuit layer PC, and overlapping the associated thin-film transistor TFT in the second pixel circuit-Examiner's annotated Fig 15),
wherein the blocking layer and the bottom metal layer are formed of a same material and
are located on a same layer (Blocking layer 610 including BML on the layer under the pixel circuit PC so on the same layer-Fig 10, [0115], [0123], [0148]).
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Regarding claim 7, Hong72 and Lee50 combination discloses all the elements of claim 1, as noted above.
Hong72 further discloses a display panel comprising:
a thin-film encapsulation layer covering the first display elements and the second display elements (thin-film encapsulation layer 300 covering first display element OLED1 in first display area DA1 and second display element OLED2 in second display area DA2-Examiner's annotated Fig 15); and
an input sensing layer located on the thin-film encapsulation layer (Input sensing layer 400 located on thin-film encapsulation layer 300-Examiner's annotated Fig 15),
wherein the blocking layer and a metal layer included in the input sensing layer are formed of a same material and are located on a same layer (blocking layer 610 including BML, and metal layer ML included in input sensing layer 400 with ML and BML in 610 being copper so the same material-Fig 10, [0115], [0123], [0148]).
Regarding claim 16, Hong72 discloses a display apparatus ([0004] L1-2) comprising:
a display panel (Title) comprising
a first display area (First display area DA1-Examiner's annotated Fig 4B) and
a second display area (Second display area DA2 including a transmission area TA-Examiner's annotated Fig 4B),
the second display area including a transmission area (Second display area DA2 including a transmission area TA-Examiner's annotated Fig 4B); and
a component located on a bottom surface of the display panel ([0016] L7-9) and
overlapping the second display area ([0016] L7-9),
wherein the display panel comprises:
a substrate (Substrate 100-Examiner's annotated Fig 4B) comprising
first display elements located in the first display area (First display elements LED located in first display area DA1 -Examiner's annotated Fig 4B) and
second display elements located in the second display area (Second display elements LED located in second display area DA2-examiner's annotated Fig 4B),
the first display elements and the second display elements
including a counter electrode integrally provided over the first display area and the second display area (Counter-electrode 230 integrally provided over first display area DA1 and second display area DA2-Examiner's annotated Fig 10)and
including at least one transmission hole located in an area corresponding to the transmission area (Counter-electrode 230 integrally provided over first display area DA1 and second display area DA2, including transmission hole 230OP corresponding to the transmission area TA-Examiner's annotated Fig 11B); and
a blocking layer at least partially overlapping an edge of the at least one transmission hole (Blocking layer 610 overlapping an edge of the transmission hole 230OP-Examiner's annotated Fig 11B).
Hong72 does not disclose a display panel
wherein the transmission area includes
a first transmission area overlapping the counter electrode and
a second transmission area overlapping the at least one transmission hole of the counter electrode in a plan view, and
each of the first transmission area and the second transmission area is exposed by the blocking layer.
Lee50 teaches a display panel (Display panel 10-Fig 4, [0058] L1-3)
wherein the transmission area (Transmission area TA indicated by the dashed line rectangle-Examiner’s annotated Fig 4) includes
a first transmission area overlapping the counter electrode (First Transmission Area overlapping counter electrode 230, as indicated by the dashed and solid line rectangular area-Examiner's annotated Fig 4) and
a second transmission area overlapping the at least one transmission hole of the counter electrode in a plan view (Second Transmission Area not overlapping counter electrode 230, as indicated by the solid line rectangular area in plan view (x,z)-Examiner's annotated Fig 4), and
each of the first transmission area and the second transmission area is exposed by the blocking layer (Blocking layer BML exposing both first and second transmission areas-Examiner's annotated Fig 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display apparatus of Hong72, as taught by Lee50 for the purpose of
reducing the image distortion (for example, flare, haze, etc.) (Lee50: [0069]).
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Regarding claim17, Hong72 and Lee50 combination discloses all the elements of claim 16, as noted above.
Hong72 further discloses a display apparatus comprising:
a pixel circuit layer located on the substrate (Pixel Circuit PC located on substrate 100-Examiner's annotated Fig 11B) and including
first pixel circuits respectively connected to the first display elements (First Pixel Circuit PC located in first display area DA1, connected to first display element OLED1-Examiner's annotated Fig 15) and
second pixel circuits respectively connected to the second display elements (Second Pixel Circuit PC located in second display area DA2, connected to second display element OLED2-Examiner's annotated Fig 15); and
a bottom metal layer located between the substrate and the pixel circuit layer (Bottom metal layer BML located between pixel circuit layer PC and substrate 100-Examiner's annotated Fig 15) and
overlapping at least one thin-film transistor included in the second pixel circuits (Bottom metal layer BML located between pixel circuit layer PC and substrate 100, at least partially overlapping second pixel circuit layer PC, and overlapping the associated thin-film transistor TFT in the second pixel circuit-Examiner's annotated Fig 15),
wherein the blocking layer and the bottom metal layer are formed of a same material and are located on a same layer (blocking layer 610 including BML, and metal layer ML included in input sensing layer 400 with ML and BML in 610 being copper so the same material, on the layer under the pixel circuit PC so on the same layer-Fig 10, [0115], [0123], [0148]).
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Regarding claim 19, Hong72 and Lee50 combination discloses all the elements of claim 16, as noted above.
Hong72 further discloses a display apparatus comprising:
a thin-film encapsulation layer covering the first display elements and the second display elements (thin-film encapsulation layer 300 covering first display element OLED1 in first display area DA1 and second display element OLED2 in second display area DA2-Examiner's annotated Fig 15); and
an input sensing layer located on the thin-film encapsulation layer (Input sensing layer 400 located on thin-film encapsulation layer 300-Examiner's annotated Fig 15),
wherein the blocking layer and a metal layer included in the input sensing layer are formed of a same material and are located on a same layer (blocking layer 610 including BML, and metal layer ML included in input sensing layer 400 with ML and BML in 610 being copper so the same material-Fig 10, [0115], [0123], [0148]).
Regarding claim 20, Hong72 and Lee50 combination discloses all the elements of claim 16, as noted above.
Hong72 further discloses a display apparatus
wherein the blocking layer is provided in a closed shape overlapping the entire edge of the at least one transmission hole (Bocking metal layer BML including an opening BML-OP so provided in a closed shape overlapping the entire edge of the transmission hole 230OP as indicated by the dashed line rectangle-Examiner's annotated Fig 11B) and
including an opening through which a central portion of the at least one transmission hole is exposed (Blocking/Bottom metal layer BML comprising opening BML-OP exposing the central portion of transmission hole 230OP-Examiner's annotated Fig 11B).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US20200373372A1 from IDS-Chung72) in view of Lee et al. (US 20230103050 A1-Lee50), and further in view of Choi et al. (US20220406867A1 from IDS-Choi67).
Regarding claim 6, Chung72 and Lee50 combination discloses all the elements of claim 4, as noted above.
Chung72 and Lee50 combination does not disclose a display panel comprising:
wherein the blocking layer is a part of a data line configured to supply a data signal to one of the second pixel circuits.
Choi67 teaches a display panel comprising:
wherein the blocking layer is a part of a data line configured to supply a data signal to one of the second pixel circuits (blocking layer BML connected to a wire receiving a constant voltage or a signal from the electrode or wire and being part of the second pixel circuit PC so being part of a data line configured to supply data signal to the second pixel circuit-Fig 6, Fig 7, [0210] L1-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display apparatus of Chung72 in view of Lee50, as taught by Choi67 for the purpose of improving the signals quality by disposing insulating layers on each sides of the blocking metal layer BML (Choi67: [0217]).
Claim(s) 12 and 14is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Chung et al. (US20200373372A1 from IDS-Chung72).
Regarding claim 12, Hong72 discloses all the elements of claim 8, as noted above.
Hong72 does not disclose a display panel comprising:
wherein at least two of
the first metal layer,
the second metal layer, and
the third metal layer
at least partially overlap the edge of the at least one transmission hole in a plan view.
Chung72 teaches a display panel comprising:
wherein at least two of
the first metal layer (First metal layer being a portion of Bottom metal layer 400 so on the same layer, including an opening 400-OP so provided in a closed shape overlapping the entire edge of the transmission hole 230OP as indicated by the dashed line rectangle, comprising opening 400-OP exposing the central portion of transmission hole 230OP-Examiner's annotated Fig 9),
the second metal layer (Second metal layer LL1 being on the same layer as electrode S of the thin-film transistor TFT in the second pixel circuit, overlapping edge of the transmission hole 230OP as indicated by the dashed line rectangle-examiner's annotated Fig 9), and
the third metal layer
at least partially overlap the edge of the at least one transmission hole in a plan view (Both first metal layer and second metal layer overlapping edge of the transmission hole 230OP as indicated by the dashed line rectangle-Examiner's annotated Fig 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Hong72, as taught by Chung72 for the purpose of preventing deterioration of image output performance even when the sensor area may be inside the display area (Chung72: [0007]).
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Regarding claim 14, Hong72 discloses all the elements of claim 8, as noted above.
Hong72 further discloses a display panel comprising:
wherein the at least one transmission hole is provided in a shape with rounded corners in a plan view (the at least one transmission hole 230OP provided in a shape with a width, so a circle so with rounded corners in Top/plan view-[0159], Fig 11A).
Hong72 does not disclose a display panel comprising:
wherein the at least one transmission hole is provided in a triangular shape with rounded corners in a plan view.
Chung72 teaches a display panel comprising:
wherein the at least one transmission hole is provided in a triangular shape with rounded corners in a plan view (the at least one transmission hole 400OP provided in a circular, oval or any other shape with rounded corners so in a triangular shape with rounded corners in a Top plan view-[0137], Fig 6A, Fig 6B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Hong72, as taught by Chung72 for the purpose of preventing deterioration of image output performance even when the sensor area may be inside the display area (Chung72: [0007]).
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Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Lee et al. (US 20230103050 A1-Lee50), and further in view of Chung et al. (US20200373372A1 from IDS-Chung72).
Regarding claim18, Hong72 and Lee50 combination discloses all the elements of claim 16, as noted above.
Hong72 further discloses a display apparatus comprising:
a pixel circuit layer located on the substrate (Pixel circuit PC on substrate 100-Examiner's annotated Fig 15) and including
first pixel circuits connected to the first display elements (First Pixel Circuit PC located in first display area DA1, connected to first display element OLED1, on substrate 100-Examiner's annotated Fig 15) and
second pixel circuits connected to the second display elements (Second Pixel Circuit PC located in second display area DA2, connected to second display element OLED2, on substrate 100-Examiner's annotated Fig 15).
Hong72 and Lee50 combination does not disclose a display apparatus
wherein the blocking layer is provided as a part of a wiring included in the pixel circuit layer.
Chung72 teaches a display apparatus
wherein the blocking layer is provided as a part of a wiring included in the pixel circuit layer (Blocking layer 400 connected to initialization voltage line VL or a power supply/Driving voltage ELVDD/ELVSS so being part of the pixel circuit layer-Fig 8, [0123]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display apparatus of Hong72 in view of Lee50, as taught by Chung72 for the purpose of preventing deterioration of image output performance even when the sensor area may be inside the display area (Chung72: [0007]).
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Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Lee et al. (US 20230036991 A1-Lee91).
Regarding claim 14, Hong72 discloses all the elements of claim 8, as noted above.
Hong72 further discloses a display panel:
wherein the at least one transmission hole is provided in a shape with rounded corners in a plan view (the at least one transmission hole 230OP provided in a shape with a width, so a circle so with rounded corners in Top/plan view-[0159], Fig 11A).
Hong72 does not disclose a display panel:
wherein the at least one transmission hole is provided in a triangular shape with rounded corners in a plan view.
Lee91 teaches a display panel:
wherein the at least one transmission hole is provided in a triangular shape with rounded corners in a plan view (the at least one transmission hole 125 opening provided in a polygonal shape with rounded corners so in a triangular shape with rounded corners in a Top plan view-[0166], Fig 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the display panel of Hong72, as taught by Lee91 for the purpose of preventing color mixing between neighboring pixels (Lee91: [0166]).
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Response to Arguments
Applicant’s arguments see pages 7-14 of Remarks, filed on 08/19/2026 with respect to claim(s) 8 have been considered but are not persuasive. Applicant’s argument focused on Hong et al. (US20230073072A1 from IDS-Hong72) having the layer 610 as being the three different metal layers when Hong72 has three distinct metal layers as seen in Updated Examiner’s annotated Hong72 Fig 11B, as discussed in the claim rejections above.
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Applicant’s arguments see pages 7-14 of Remarks, filed on 08/19/2026 with respect to the 35 U.S.C 102 rejection of claims 1 and 16 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claims 1, 8, and 16 have been amended to further define the claimed subject matter see pages 4-14 of Amendments to Claims, filed on 08/19/2026.
Claim(s) 8-11, 13, 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. (US20230073072A1 from IDS-Hong72), as noted above.
Therefore, claim(s) 8-11, 13, 15 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. (US20230073072A1 from IDS-Hong72).
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US20200373372A1 from IDS-Chung72) in view of Lee et al. (US 20230103050 A1-Lee50), as noted above.
Therefore, claim(s) 1-5 stand rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US20200373372A1 from IDS-Chung72) in view of Lee et al. (US 20230103050 A1-Lee50).
Claim(s) 1-2, 7, 16-17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Lee et al. (US 20230103050 A1-Lee50), as noted above.
Therefore, claim(s) 1-2, 7, 16-17, 19-20 stand rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Lee et al. (US 20230103050 A1-Lee50).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US20200373372A1 from IDS-Chung72) in view of Lee et al. (US 20230103050 A1-Lee50), and further in view of Choi et al. (US20220406867A1 from IDS-Choi67), as noted above.
Therefore, claim(s) 6 stands rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US20200373372A1 from IDS-Chung72) in view of Lee et al. (US 20230103050 A1-Lee50), and further in view of Choi et al. (US20220406867A1 from IDS-Choi67).
Claim(s) 12 and 14is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Chung et al. (US20200373372A1 from IDS-Chung72), as noted above.
Therefore, claim(s) 12 and 14 stand rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Chung et al. (US20200373372A1 from IDS-Chung72).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Lee et al. (US 20230103050 A1-Lee50), and further in view of Chung et al. (US20200373372A1 from IDS-Chung72), as noted above.
Therefore, claim(s) 18 stands rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Lee et al. (US 20230103050 A1-Lee50), and further in view of Chung et al. (US20200373372A1 from IDS-Chung72).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Lee et al. (US 20230036991 A1-Lee91), as noted above.
Therefore, claim(s) 14 stands rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (US20230073072A1 from IDS-Hong72) in view of Lee et al. (US 20230036991 A1-Lee91).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 09/09/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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