Prosecution Insights
Last updated: July 17, 2026
Application No. 18/660,264

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102
Filed
May 10, 2024
Examiner
ERDEM, FAZLI
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
918 granted / 1075 resolved
+25.4% vs TC avg
Strong +16% interview lift
Without
With
+15.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
36 currently pending
Career history
1099
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
62.4%
+22.4% vs TC avg
§102
30.5%
-9.5% vs TC avg
§112
3.7%
-36.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1075 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhu et al. (20110133299). Regarding Claim 1, in Figs 1-3 and 5 and in paragraphs 0004, 0010, 0023, 0025, 0027, 0028, 0030, 0032-0034 Zhu et al. discloses a semiconductor memory structure, comprising a bottom electrode, a base stack stacking on the bottom electrode along a first direction, a magnetic stack stacking on the base stack along the first direction and comprising two or more free layers separated by one or more spacer layers, wherein each of the one or more spacer layers is sandwiched by two of the two or more free layers, and wherein the spacer layers include a metal oxide; a capping layer formed on an uppermost free layer of the two or more free layers of the magnetic stack; and a top electrode formed on the capping layer. Regarding Claim 2, in Zhu et al, the one or more spacer layers include magnesium oxide, silicon oxide, strontium titanium oxide, barium titanium oxide, calcium titanium oxide, lanthanum aluminum oxide, manganese oxide, vanadium oxide, aluminum oxide, titanium oxide, or hafnium oxide. Regarding Claim 3, in Zhu et al., the one or more spacer layers include magnesium oxide (MgO), wherein Mg content is about 40 atomic % to about 60 atomic % and O content is about 40 atomic % to about 60 atomic %. Regarding Claim 4, in Zhu et al, each of the one or more spacer layers has a thickness equal to or less than about 1 nm. Regarding Claim 5, in Zhu et al, each of the one or more spacer layers has a thickness ranging from about 1 Angstroms to about 100 Angstroms. Regarding Claim 6, in Zhu et al., the base stack comprises: a seed layer disposed over the bottom electrode; a reference layer disposed over the seed layer; and a barrier layer disposed over the reference layer, wherein a lowest free layer of the two or more free layers of the magnetic stack is formed on the barrier layer. Regarding Claim 7, in Zhu et al, wherein the barrier layer includes a metal oxide. Regarding Claim 8, in Zhu et al, the barrier layer is comprised of MgO and the one or more spacer layers are comprised of MgO. Regarding Claim 9, in Figs 1-3 and 5 and in paragraphs 0004, 0010, 0023, 0025, 0027, 0028, 0030, 0032-0034 Zhu et al. discloses a magnetic tunnel junction (MTJ) structure, comprising a magnetic stack stacking on a base stack and comprising: a bottom free layer; a first spacer layer formed on the bottom free layer and including a metal oxide; and a top free layer formed over the first spacer layer, wherein a ratio of a thickness of the bottom free layer to a thickness of the first spacer layer ranges from about 5 to about 50; and a ratio of a thickness of the top free layer to the thickness of the first spacer layer ranges from about 5 to about 50. Regarding Claim 10, in Zhu et al, one or more internal free layers formed over the first spacer layer; one or more second spacer layers separating the internal free layers and including a metal oxide; and a third spacer layer formed on an uppermost internal free layer to separate the uppermost internal free layer from the top free layer. Regarding Claim 11, in Zhu et al, the first spacer layer, the one or more second spacer layers and the third spacer layer include magnesium oxide, silicon oxide, strontium titanium oxide, barium titanium oxide, calcium titanium oxide, lanthanum aluminum oxide, manganese oxide, vanadium oxide, aluminum oxide, titanium oxide, or hafnium oxide. Regarding Claim 12, in Zhu et al, the first spacer layer, the one or more second spacer layers and the third spacer layer include magnesium oxide (MgO), wherein Mg content is about 50 atomic % and O content is about 50 atomic %. Regarding Claim 13, in Zhu et al, each of the first spacer layer, the one or more second spacer layers and the third spacer layer has a thickness equal to or less than about 3 Angstroms. Regarding Claim 14, in Zhu et al, wherein each of the first spacer layer, the one or more second spacer layers and the third spacer layer has a same thickness. Regarding Claim 15, in Figs 1-3 and 5 and in paragraphs 0004, 0010, 0023, 0025, 0027, 0028, 0030, 0032-0034 Zhu et al. discloses a method of manufacturing a semiconductor memory structure, comprising forming a base stack on a bottom electrode including sequentially depositing a seed layer, a reference layer and a barrier layer; forming a magnetic stack on the base stack comprising: forming two or more free layers over the base stack on the barrier layer of the base stack; and forming one or more spacer layers between each two of the two or more free layers; forming a capping layer on the magnetic stack; and forming a top electrode on the capping layer, wherein the one or more spacer layers include metal oxides. Regarding Claim 16, in Zhu et al, wherein forming one or more spacer layers comprises: sputtering a metal material on each of the two or more free layer; and performing an oxidation process to oxidize the metal material to form the metal oxides. Regarding Claim 17, in Zhu et al, wherein forming one or more spacer layers comprises depositing a metal oxide on each of the two or more free layer. Regarding Claim 18, in Zhu et al, wherein forming one or more spacer layers comprises: depositing a first metal layer on each of the two or more free layer; and depositing a second metal layer on the first metal layer followed by an oxidation process. Regarding Claim 19, in Zhu et al, the one or more spacer layers include magnesium oxide (MgO). Regarding Claim 20, in Zhu et al, each of the one or more spacer layers has a thickness ranging from about 1 Angstroms to about 100 Angstroms. Examiner is including Erickson 20160005954, Jung 20130032911, Watts 20140151829 and Zhang et al. (20110293967) as pertinent prior art references that are not applied on this rejection but that disclose free layer/spacer layer (MgO) stacks and/or perpendicular anisotropy modulation Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 5/31/2026
Read full office action

Prosecution Timeline

May 10, 2024
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+15.9%)
2y 5m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1075 resolved cases by this examiner. Grant probability derived from career allowance rate.

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