DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species 1 in the reply filed on August 24, 2026 is acknowledged.
Claim Objections
Regarding claim 14, lines 8 and 10 refer to “ninth” and “tenth” gate electrodes extending across fifth and sixth active areas. However, claim 12 regards these gate electrodes as “fifth” and “sixth” gate electrodes in the same location. This reflects a labeling change across claims, thus it is suggested that one particular nomenclature is chosen for consistency.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding claim 5, line 9 recites the limitation that, “the sixth gate electrode is electrically connected to the fourth word line.” However, this does not align with the claim language of claim 2. It is suggested that “the sixth gate electrode” in line 9 reads “the fourth gate electrode” to provide clarity.
Regarding claim 15, lines 4-6 recite, “a first via extending from one of the first through fourth bit lines to the corresponding one of the first through fourth active areas adjacent to a first side of one of the first through sixth gate electrodes.” It is unclear what should be “adjacent to a first side” because this could refer to the via or the active area. Further, it is unclear which orientation is the reference for “a side of” the electrodes, whether in the two-dimensional plane or the Z-direction. For the purpose of examination, it is assumed the via is adjacent to a side of the electrode in the X-direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (2021/0202503, hereafter Chang) in view of Scott et al. (2008/0123388, hereafter Scott).
Regarding claim 1, Chang discloses a read-only memory (ROM) array comprising: first through fourth rows of ROM bits (par. 0127) comprising respective first through fourth adjacent active areas (AA1 – AA4), wherein each of the first through fourth rows of ROM bits comprises a total of four adjacent ROM bits (SD1/SD2, SD5/SD6, SD13/SD14, SD9/SD10) positioned along the corresponding one of the first through fourth active areas, each ROM bit of the total of four ROM bits of each row of ROM bits comprises two source/drain (S/D) regions (SD1 – SD32) in the corresponding active area (Fig. 7).
Chang fails to disclose three of the S/D regions of each row of ROM bits are shared by the four ROM bits.
However, Scott teaches three of the S/D regions of each row of ROM bits are shared by the four ROM bits (Fig. 2, par. 0022-0023).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang with Scott by providing shared regions for source/drain bits in order to reduce area required for the device, increasing memory density and manufacturing yield.
Regarding claim 2, Chang discloses a ROM array further comprising: a first gate electrode (G1) shared by the first ROM bit (SD1/SD2) of each of the first through fourth rows of ROM bits (AA1 – AA4); a second gate electrode (G2) shared by the second ROM bit (SD5/SD6) of each of the first through fourth rows of ROM bits; a third gate electrode (G4) shared by the third ROM bit (SD13/SD14) of each of the first and second rows of ROM bits; a fourth gate electrode (G3) shared by the fourth ROM bit (SD10/SD9) of each of the first and second rows of ROM bits; a fifth gate electrode (G4 lower) shared by the third ROM bit (SD14/SD13) of each of the third and fourth rows of ROM bits; and a sixth gate electrode (G3C/G3D) shared by the fourth ROM bit (SD10/SD9) of each of the third and fourth rows of ROM bits (Fig. 7).
Regarding claim 3, Chang fails to explicitly disclose a ROM array of wherein each of the first through fourth active areas extends between first and second dummy gate structures, the first and second dummy gate structures and first through sixth gate electrodes are spaced apart in accordance with a gate pitch, and the first and second dummy gate structures (ends) are separated by distance corresponding to five times the gate pitch.
However, in another embodiment, Chang teaches a ROM array of wherein each of the first through fourth active areas (AA1-AA4) extends between first and second dummy gate structures (par. 0042), the first and second dummy gate structures and first through sixth gate electrodes are spaced apart in accordance with a gate pitch (distance between G1 and G2), and the first and second dummy gate structures (ends) are separated by distance corresponding to five times the gate pitch (Fig. 7).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang by providing dummy gates at the ends in order to maintain structural and optical uniformity during manufacturing, preventing performance degradation effects.
Regarding claim 4, Chang fails to explicitly disclose a ROM array further comprising: a first isolation structure positioned between the third and fifth gate electrodes; and a second isolation structure positioned between the fourth and sixth gate electrodes.
However, in another embodiment, Chang teaches a ROM array further comprising: a first isolation structure (CP4) positioned between the third (G4 upper, par. 0078) and fifth gate (G4 lower, par. 0078) electrodes; and a second isolation structure (CP4) positioned between the fourth (G3A/G3B) and sixth (G3C/G3D) gate electrodes (Fig. 7).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang by providing an isolation structure across multiple gates in order to maintain uniform patterning across an active array, preventing distortion and simplifying isolation during manufacturing.
Regarding claim 5, Chang fails to explicitly disclose a ROM array wherein the first gate electrode is electrically connected to a first word line exclusively through a first gate via positioned between the third and fourth active areas, the second gate electrode is electrically connected to a second word line exclusively through a second gate via positioned between the first and second active areas, the fifth gate electrode is electrically connected to a third word line exclusively through a third gate via positioned between the third and fourth active areas, and the sixth gate electrode is electrically connected to a fourth word line exclusively through a fourth gate via positioned between the first and second active areas.
However, in another embodiment, Chang teaches a ROM array wherein the first gate electrode (G1) is electrically connected to a first word line (MS3) exclusively through a first gate via (VG1) positioned between the third (AA3) and fourth (AA4) active areas (Fig. 7), the second gate electrode (G2) is electrically connected to a second word line (MS5) exclusively through a second gate via (VG3) positioned between the first (AA4) and second (AA5) active areas (Fig. 11), the fifth gate electrode (G3 lower) is electrically connected to a third word line (MS4) exclusively through a third gate via (VG2) positioned between the third and fourth active areas (Fig. 8), and the sixth gate electrode (G3B/G3C) is electrically connected to a fourth word line (MS4) exclusively through a fourth gate via (VG2) positioned between the first and second active areas (Fig. 7).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang by providing word lines and vias in various positions with respect to the gate structures in order to relieve layout constraints, preventing shorting and allowing easier manufacturing.
Regarding claim 6, Chang discloses ROM array further comprising: fifth through eighth rows of ROM bits comprising respective fifth through eighth adjacent active areas (AA5 – AA8, Fig. 11), wherein the fifth active area is adjacent to the fourth active area, each of the fifth through eighth rows of ROM bits comprises a total of four adjacent ROM bits (SD1/SD2, SD5/SD6, SD13/SD14, SD9/SD10, Fig. 5, 11) positioned along the corresponding one of the fifth through eighth active areas.
Chang fails to explicitly disclose the fifth gate electrode is further shared by the third ROM bit of each of the fifth and sixth rows of ROM bits, and the sixth gate electrode is further shared by the fourth ROM bit of each of the fifth and sixth rows of ROM bits a seventh gate electrode shared by the first ROM bit of each of the fifth through eighth rows of ROM bits; an eighth gate electrode shared by the second ROM bit of each of the fifth through eighth rows of ROM bits; a ninth gate electrode shared by the third ROM bit of each of the seventh and eighth rows of ROM bits and a tenth gate electrode shared by the fourth ROM bit of each of the seventh and eighth rows of ROM bits.
However, in another embodiment, Chang teaches the fifth gate electrode (G4 lower middle, Fig. 11) is further shared by the third ROM bit (SD13/SD14) of each of the fifth and sixth rows of ROM bits (AA5, AA6), and the sixth gate electrode (G3 lower middle) is further shared by the fourth ROM (SD9/SD10) bit of each of the fifth and sixth rows of ROM bits (AA5 – AA6); a seventh gate electrode (G1 lower) shared by the first ROM bit (SD1/SD2) of each of the fifth through eighth rows of ROM bits; an eighth gate electrode (G2 lower) shared by the second ROM bit (SD5/SD6) of each of the fifth through eighth rows of ROM bits; a ninth gate electrode (G4 lower) shared by the third ROM bit of each of the seventh and eighth rows of ROM bits (AA7 – AA8); and a tenth gate electrode (G3 lower) shared by the fourth ROM bit of each of the seventh and eighth rows of ROM bits (Fig. 11).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang by providing an isolation structure across multiple gates in order to maintain uniform patterning across an active array, preventing distortion and simplifying isolation during manufacturing.
Regarding claim 8, Chang discloses a ROM array further comprising: fifth through eighth rows of ROM bits comprising respective fifth through eighth adjacent active areas (AA5 – AA8, Fig. 11) aligned with the respective first through fourth active areas, wherein each of the fifth through eighth rows of ROM bits comprises a total of four adjacent ROM bits (SD1/SD2, SD5/SD6, SD13/SD14, SD9/SD10, Fig. 5, 11) positioned along the corresponding one of the fifth through eighth active areas, each ROM bit of the total of four ROM bits of each of the fifth through eighth rows of ROM bits comprises two S/D regions in the corresponding active area.
Chang fails to disclose three of the S/D regions of each of the fifth through eighth rows of ROM bits are shared by the four ROM bits.
However, Scott teaches three of the S/D regions of each of the fifth through eighth rows of ROM bits are shared by the four ROM bits (Fig. 2, par. 0022-0023).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang with Scott by providing shared regions for source/drain bits in order to reduce area required for the device, increasing memory density and manufacturing yield.
Regarding claim 21, Chang discloses a read-only memory (ROM) array comprising: first through fourth rows of ROM bits (par. 0127) comprising respective first through fourth adjacent active areas (AA1 – AA4, Fig. 7) and first through sixth gate electrodes, wherein a first ROM bit of each of the first through fourth rows of ROM bits comprises the first gate electrode (G1), a second ROM bit of each of the first through fourth rows of ROM bits comprises the second gate electrode (G2) and a first source/drain (S/D) region (SD1/SD2) of the corresponding active area…, a third ROM bit of each of the first and second rows of ROM bits comprises the third gate electrode (G4 upper) and…, a fourth ROM bit of each of the first and second rows of ROM bits comprises the fourth gate electrode (G3 upper) and…, a third ROM bit of each of the third and fourth rows of ROM bits comprises the fifth gate electrode (G4 lower) and…, a fourth ROM bit of each of the third and fourth rows of ROM bits comprises the sixth gate electrode (G3 lower) (Fig. 7).
Chang fails to disclose shared with the corresponding first ROM bit, a second S/D region of the corresponding active area shared with the corresponding second ROM bit, a third S/D region of the corresponding active area shared with the corresponding third ROM bit, a second S/D region of the corresponding active area shared with the corresponding second ROM bit, and a third S/D region of the corresponding active area shared with the corresponding third ROM bit.
However, Scott teaches shared with the corresponding first ROM bit (Fig. 2, par. 0022-0023), a second S/D region of the corresponding active area shared with the corresponding second ROM bit (Fig. 2, par. 0022-0023), a third S/D region of the corresponding active area shared with the corresponding third ROM bit (Fig. 2, par. 0022-0023), a second S/D region of the corresponding active area shared with the corresponding second ROM bit (Fig. 2, par. 0022-0023), and a third S/D region of the corresponding active area shared with the corresponding third ROM bit (Fig. 2, par. 0022-0023).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang with Scott by providing shared regions for source/drain bits in order to reduce area required for the device, increasing memory density and manufacturing yield.
Regarding claim 22, Chang discloses a ROM array further comprising: a first via (VG1, Fig. 11) electrically connected to the first gate electrode (G1) between the third and fourth active areas (AA2, AA3); a second via (VG3) electrically connected to the second gate electrode (G2) between the first and second active areas (AA4, AA5).
Chang fails to explicitly disclose a third via electrically connected to the fifth gate electrode between the third and fourth active areas; and a fourth via electrically connected to the fourth gate electrode between the first and second active areas.
However, in another embodiment, Chang teaches a third via (VG6, Fig. 11) electrically connected to the fifth gate electrode (G4 lower) between the third and fourth active areas; and a fourth via (VG5) electrically connected to the fourth gate electrode (G3 upper) between the first and second active areas (Fig. 11).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang by providing vias in various positions with respect to the gate structures in order to relieve layout constraints, preventing shorting and allowing easier manufacturing.
Regarding claim 23, Chang discloses a ROM array further comprising: first through fourth metal segments (MS3, MS5, MS10, MS9) in a first metal layer electrically connected to the respective first through fourth vias (VG1, VG3, VG6, VG5) (Fig. 11).
Claims 9, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Scott as applied to claims 1 and 21 above, and further in view of Lu et al. (2019/0043587, hereafter Lu).
Regarding claim 9, Chang and Scott, discussed above, fail to disclose a ROM array further comprising: first through fourth bit lines and first through fourth source lines overlying the respective first through fourth rows of ROM bits wherein at last one ROM bit of the four ROM bits of the first through fourth rows of ROM bits comprises: a first via extending from one of the two S/D regions to a corresponding one of the first through fourth bit lines; and a second via extending from the other of the two S/D regions to a corresponding one of the first through fourth source lines.
However, Lu teaches a ROM array further comprising: first through fourth bit lines (BL, Fig. 1) and first through fourth source lines (SL, Fig. 1) overlying the respective first through fourth rows of ROM bits (S/D, Fig. 2), wherein at last one ROM bit of the four ROM bits of the first through fourth rows of ROM bits comprises: a first via extending from one of the two S/D regions to a corresponding one of the first through fourth bit lines (BC/SC, Fig. 2); and a second via extending from the other of the two S/D regions to a corresponding one of the first through fourth source lines (BC/SC, Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang and Scott with Lu by providing bit and source lines underlying the rows and including staggered vias connecting the layers in order to minimize layout constraints and resistance as well as eliminating spatial congestion.
Regarding claim 24, Chang discloses metal segments (MS1) each of the first through fourth gate electrodes (G1 – G4) (Fig. 11) and metal segments (MS2) each of the first, second, fifth, and sixth gate electrodes (G1, G2, G4 lower, G3 lower) (Fig. 11).
Chang and Scott fail to disclose a ROM array, further comprising: fifth and sixth metal segments in the first metal layer overlying the first active area; seventh and eighth metal segments in the first metal layer overlying the second active area; ninth and tenth metal segments in the first metal layer overlying the third active area; and eleventh and twelfth metal segments in the first metal layer overlying the fourth active area.
However, Lu teaches a ROM array, further comprising: fifth and sixth metal segments (BL/SL, Fig. 2) in the first metal layer overlying the first active area (102)…; seventh and eighth metal segments in the first metal layer overlying the second active area (Fig. 2)…; ninth and tenth metal segments in the first metal layer overlying the third active area (Fig. 2); and eleventh and twelfth metal segments in the first metal layer overlying the fourth active area (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang and Scott with Lu by providing bit and source lines underlying the rows and including staggered vias connecting the layers in order to minimize layout constraints and resistance as well as eliminating spatial congestion.
Regarding claim 25, Chang and Scott fail to disclose a ROM array further comprising: at least one fifth via electrically connected to one of the fifth through twelfth metal segments and one of the first through third S/D regions of the corresponding first, second, third, or fourth active area.
However, Lu teaches a ROM array further comprising: at least one fifth via (BC/SC) electrically connected to one of the fifth through twelfth metal segments and one of the first through third S/D regions of the corresponding first, second, third, or fourth active area (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang and Scott with Lu by providing vias connecting the layers in order to minimize layout constraints and resistance as well as eliminating spatial congestion.
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chang.
Regarding claim 10, Chang discloses an integrated circuit (IC) device comprising: first through fourth adjacent active areas (AA1 – AA4) extending between first and second dummy gate structures (par. 0042); a first gate electrode (G1, Fig. 7) extending across each of the first through fourth active areas and offset from the first dummy gate structure by a gate pitch; a second gate electrode (G2) extending across each of the first through fourth active areas and offset from the first gate electrode by the gate pitch; a third gate electrode (G4 upper) extending across each of the first and second active areas and offset from the second gate electrode by the gate pitch; a fourth gate electrode (G3 upper) extending across each of the first and second active areas and offset from each of the third gate electrode and the second dummy gate structure by the gate pitch (Fig. 7).
Chang fails to explicitly disclose a fifth gate electrode extending across each of the third and fourth active areas, offset from the second gate electrode by the gate pitch, and separated from the third gate electrode by a first isolation structure; and a sixth gate electrode extending across each of the third and fourth active areas, offset from each of the fifth gate electrode and the second dummy gate structure by the gate pitch, and separated from the fourth gate electrode by a second isolation structure.
However, in an embodiment Chang teaches a fifth gate electrode (G4 lower, Fig. 7) extending across each of the third and fourth active areas, offset from the second gate electrode by the gate pitch, and separated from the third gate electrode by a first isolation structure (CP2, Fig. 7); and a sixth gate electrode (G3 lower, Fig. 7) extending across each of the third and fourth active areas, offset from each of the fifth gate electrode and the second dummy gate structure by the gate pitch, and separated from the fourth gate electrode by a second isolation structure (CP2, Fig. 7).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang by providing an isolation structure across multiple gates in order to maintain uniform patterning across an active array, preventing distortion and simplifying isolation during manufacturing.
Regarding claim 11, Chang fails to explicitly disclose a IC device further comprising: a first metal segment positioned between the third and fourth active areas in a first metal layer and electrically connected to the first gate electrode through a first gate via a second metal segment positioned between the third and fourth active areas in the first metal layer and electrically connected to the fifth gate electrode through a second gate via a third metal segment positioned between the first and second active areas in the first metal layer and electrically connected to the second gate electrode through a third gate via and a fourth metal segment positioned between the first and second active areas in the first metal layer and electrically connected to the fourth gate electrode through a fourth gate via.
However, in an embodiment, Chang teaches a IC device further comprising: a first metal segment (MS3, Fig. 11) positioned between the third and fourth active areas in a first metal layer and electrically connected to the first gate electrode (G1) through a first gate via (VG1); a second metal segment (MS10, Fig. 11) positioned between the third and fourth active areas in the first metal layer and electrically connected to the fifth gate electrode (G4 lower) through a second gate via (VG6); a third metal segment (MS5, Fig. 11) positioned between the first and second active areas in the first metal layer and electrically connected to the second gate electrode (G2) through a third gate via (VG3); and a fourth metal segment (MS4, Fig. 11) positioned between the first and second active areas in the first metal layer and electrically connected to the fourth gate electrode (G3 upper) through a fourth gate via (VG2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang by providing metal segments and vias in various positions with respect to the gate structures in order to relieve layout constraints, preventing shorting and allowing easier manufacturing.
Regarding claim 12, Chang discloses a IC device further comprising: fifth through eighth adjacent active areas (AA5 – AA8, Fig. 11) extending between the first and second dummy gate structures (par. 0042), wherein the fifth active area is adjacent to the fourth active area, and each of the fifth and sixth gate electrodes (G4/G3 middle) extends across the fifth and sixth active areas; a seventh gate electrode (G1 lower) extending across each of the fifth through eighth active areas, aligned with the first gate electrode, and separated from the first gate electrode by a third isolation structure (CP3); an eighth gate electrode (G2 lower) extending across each of the fifth through eighth active areas, aligned with the second gate electrode, …a ninth gate electrode (G4 lower) extending across each of the seventh and eighth active areas, aligned with the fifth gate electrode, …a tenth gate electrode (G3 lower) extending across each of the seventh and eighth active areas, aligned with the sixth gate electrode, and separated from the sixth gate electrode by a sixth isolation structure (CP6) (Fig. 11).
Chang fails to explicitly disclose separated from the second gate electrode by a fourth isolation structure; and separated from the fifth gate electrode by a fifth isolation structure; a fifth metal segment positioned between the seventh and eighth active areas in the first metal layer and electrically connected to the first metal segment and to the seventh gate electrode through a fifth gate via a sixth metal segment positioned between the seventh and eighth active areas in the first metal layer and electrically connected to the second metal segment and to the ninth gate electrode through a sixth gate via a seventh metal segment positioned between the fifth and sixth active areas in the first metal layer and electrically connected to the third metal segment and to the eighth gate electrode through a seventh gate via and an eighth metal segment positioned between the fifth and sixth active areas in the first metal layer and electrically connected to the fourth metal segment and to the sixth gate electrode through an eighth gate via.
However, in an embodiment, Chang teaches separated from the second gate electrode by a fourth isolation structure (CP3, Fig. 11); and separated from the fifth gate electrode by a fifth isolation structure (CP4, Fig. 11); a fifth metal segment (MS8, Fig. 11) positioned between the seventh and eighth active areas in the first metal layer and electrically connected to the first metal segment (MS3) and to the seventh gate electrode (G1 lower) through a fifth gate via (VG4); a sixth metal segment (MS10) positioned between the seventh and eighth active areas in the first metal layer and electrically connected to the second metal segment and to the ninth gate electrode (G4 lower) through a sixth gate via (VG6); a seventh metal segment (MS9) positioned between the fifth and sixth active areas in the first metal layer and electrically connected to the third metal segment (MS4) and to the eighth gate electrode (G3 lower) through a seventh gate via (VG5); and an eighth metal segment (MS9) positioned between the fifth and sixth active areas in the first metal layer and electrically connected to the fourth metal segment (MS4) and to the sixth gate electrode (G3 middle) through an eighth gate via (VG5) (Fig. 11).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang by providing an isolation structure across multiple gates in order to maintain uniform patterning across an active array, preventing distortion and simplifying isolation during manufacturing, and providing metal segments and vias in various positions with respect to the gate structures in order to relieve layout constraints, preventing shorting and allowing easier manufacturing.
Regarding claim 14, Chang discloses a IC device further comprising: fifth through eighth adjacent active areas (AA5 – AA8, Fig. 11) extending between third and fourth dummy gate structures (par. 0042) and aligned with the respective first through fourth active areas; a seventh gate electrode (G1 lower) extending across each of the fifth through eighth active areas and offset from the third dummy gate structure by the gate pitch; an eighth gate electrode (G2 lower) extending across each of the fifth through eighth active areas and offset from the seventh gate electrode by the gate pitch; a ninth gate electrode (G4 lower) extending across each of the fifth and sixth active areas and offset from the eighth gate electrode by the gate pitch; a tenth gate electrode (G3 lower) extending across each of the fifth and sixth active areas and offset from each of the ninth gate electrode and the fourth dummy gate structure by the gate pitch.
Chang fails to explicitly disclose an eleventh gate electrode extending across each of the seventh and eighth active areas, offset from the eighth gate electrode by the gate pitch, and separated from the ninth gate electrode by a third isolation structure and a twelfth gate electrode extending across each of the seventh and eighth active areas, offset from each of the eleventh gate electrode and the fourth dummy gate structure by the gate pitch, and separated from the tenth gate electrode by a fourth isolation structure.
However, in an embodiment Chang teaches an eleventh gate electrode (G4 lower, Fig. 11) extending across each of the seventh and eighth active areas, offset from the eighth gate electrode (G2 lower) by the gate pitch, and separated from the ninth gate electrode (G4 upper middle) by a third isolation structure (CP5); and a twelfth gate electrode (G3 lower) extending across each of the seventh and eighth active areas, offset from each of the eleventh gate electrode and the fourth dummy gate structure by the gate pitch, and separated from the tenth gate electrode (G3 upper middle) by a fourth isolation structure (CP5 extended) (Fig. 11).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang by providing an isolation structure across multiple gates in order to maintain uniform patterning across an active array, preventing distortion and simplifying isolation during manufacturing.
Claim 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Lu.
Regarding claim 15, Chang, discussed above, fails to disclose a IC device further comprising: first through fourth bit lines and first through fourth source lines positioned in the first metal layer overlying the respective first through fourth active areas; a first via extending from one of the first through fourth bit lines to the corresponding one of the first through fourth active areas adjacent to a first side of one of the first through sixth gate electrodes; and a second via extending from the corresponding one of the first through fourth source lines to the corresponding one of the first through fourth active areas adjacent to a second side of the one of the first through sixth gate electrodes.
However, Lu teaches a IC device further comprising: first through fourth bit lines (BL, Fig. 1) and first through fourth source lines (SL, Fig. 1) positioned in the first metal layer overlying the respective first through fourth active areas (102, Fig. 2); a first via (BC/SC, Fig. 2) extending from one of the first through fourth bit lines to the corresponding one of the first through fourth active areas adjacent to a first side of one of the first through sixth gate electrodes; and a second via extending from the corresponding one of the first through fourth source lines to the corresponding one of the first through fourth active areas adjacent to a second side of the one of the first through sixth gate electrodes (Fig. 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Chang with Lu by providing bit and source lines underlying the rows and including staggered vias connecting the layers in order to minimize layout constraints and resistance as well as eliminating spatial congestion.
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/C.M.B./ Examiner, Art Unit 2817
/ALI NARAGHI/ Primary Examiner, Art Unit 2817
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