DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-13 and 17-20 in the reply filed on 07/24/26 is acknowledged.
Newly submitted claims 21-23 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: The claims are drawn to another semiconductor device that
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-23 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/13/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the "a ratio of the second pattern density to the first pattern density is between 20 and 200" must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 17, and 19 are rejected under U.S.C. 103 as being unpatentable over Kim; US 2020/0013764 A1; 01/2019 in view of Song et al.; US 2024/0088055 A1; 09/2023
Claim 1: Kim(‘764) discloses a semiconductor package, comprising: a semiconductor device ( Fig. 2B #200 ); a molding material ( Fig. 2B #300 ) laterally surrounding the semiconductor device; and an alignment mark ( Fig. 2B #540 ) comprising a first through-molding-via (TMV) and a second TMV, each formed in the molding material ( as shown in Fig. 2B ).
Kim(‘764) does not appear to disclose the first TMV comprises a first specific dimension and the second TMV comprises a second specific dimension that is larger than the first specific dimension.
However, Song teaches the first TMV comprises a first specific dimension ( Fig. 2 128a ) and the second TMV comprises a second specific dimension ( Fig. 2 128b ) that is larger than the first specific dimension ( as shown in Fig. 2 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song with Kim(‘764) to implement the first TMV comprises a first specific dimension and the second TMV comprises a second specific dimension that is larger than the first specific dimension because this approach enables reliable plating and filling.
Claim 2: Kim(‘764) and Song disclose the semiconductor package of claim 1 ( as described above ).
Kim(‘764) teaches the semiconductor package comprises a rectangular geometry ( Fig. 1 #200 ) and the alignment mark ( Fig. 2B #540 ) is located near a corner of the semiconductor package ( as shown in Fig. 2B ).
Claim 10: Kim (‘764) and Song disclose the semiconductor package of claim 9 ( as discussed above ).
Kim (‘764) does not appear to disclose the first specific dimension is between 10 microns and 150 microns; and the second specific dimension is between 100 microns and 500 microns.
However, Song teaches the first specific dimension is between 10 microns and 150 microns ( [0050] A size of the angled first alignment mark 128a may be X1 and Y1 in X and Y directions, respectively. In some embodiments, each of X1 and Y1 may be 100 μm to 400 μm ) ; and the second specific dimension is between 100 microns and 500 microns ( as discussed above ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song with Kim(‘764) to implement the first specific dimension is between 10 microns and 150 microns; and the second specific dimension is between 100 microns and 500 microns because this approach balances resistance, reliability, and routing density.
Claim 17: Kim (‘764 ) discloses a method of forming a semiconductor package ( Figs. 2A to 2H ), comprising: forming a plurality of conductive vias ( Fig. 2C alignment structures 540 ) over a substrate ( Fig. 2C substrate 100 ) including an alignment mark comprising a first conductive via ( Fig. 2C #540 right side of figure ) and a second conductive via ( Fig. 2C #540 left side of figure ); positioning a semiconductor device ( as shown in Fig. 2C ) over the substrate ( Fig. 2C #10 ) and aligning the semiconductor device ( Fig. 2H #730 ) relative to the alignment mark ( Fig. 2C #540; blow up image in Fig. 5 ) ; attaching the semiconductor device ( Fig. 2H #730 ) to the substrate ( Fig. 2C #100 ); and forming a molding material ( Fig. 2H #750 ) around the semiconductor device ( Fig. 2H #730 ) and the plurality of conductive vias ( Fig. 2H #540 is covered by molding #300 ) such that the plurality of conductive vias comprise a corresponding plurality of through-molding-vias (TMVs) ( as shown in Fig. 2H ).
Kim (‘764) does not appear to disclose the first conductive via comprises a first specific dimension and the second conductive via comprises a second specific dimension that is greater than the first specific dimension;
However, Song teaches the first conductive via comprises a first specific dimension ( Fig. 2 128a ) and the second conductive via comprises a second specific dimension ( Fig. 2 128b ) that is greater than the first specific dimension ( as shown in Fig. 2 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Song with Kim(‘764) to implement the first conductive via comprises a first specific dimension and the second conductive via comprises a second specific dimension that is greater than the first specific dimension because this approach enables reliable plating and filling.
Claim 19: Kim (‘764) and Song disclose the method of claim 17 ( as discussed above ).
Kim (‘764) teaches forming the plurality of conductive vias further comprises: forming the plurality of conductive vias to be configured in a rectangular arrangement around a perimeter of a first rectangular region ( as shown in Fig. 1 #540 ), and wherein attaching the semiconductor device to the substrate further comprises positioning, aligning, and attaching the semiconductor device to the substrate within the first rectangular region ( as described in Figs. 2A-2H ).
Claims 3, 9, and 13 are rejected under U.S.C. 103 as being unpatentable over Kim; US 2020/0013764 A1; 01/2019 in view of Song et al.; US 2024/0088055 A1; 09/2023 as it relates to claim 1 above and further in view of Shin et al.; US 2008/0073782 A1; 07/2007
Claim 3: Kim(‘764) and Song disclose the semiconductor package of claim 1 ( as discussed above ).
Neither Kim(‘764) nor Song appear to disclose the alignment mark further comprises: one or more first TMVs located in a first region; and one or more second TMVs located in a second region that surrounds the first region.
However, Shin teaches the alignment mark further comprises: one or more first TMVs located in a first region ( Fig. 3B #233 ) ; and one or more second TMVs ( Fig. 3B #133 ) located in a second region that surrounds the first region ( as shown in Fig. 3B ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Shin with Kim(‘764) and Song to implement the alignment mark further comprises: one or more first TMVs located in a first region; and one or more second TMVs located in a second region that surrounds the first region because this approach provides coaxial electromagnetic interference (EMI) shielding and controlled impedance.
Claim 9: Kim (‘764), Song, and Shin disclose the semiconductor package of claim 3 ( as discussed above ).
Kim (‘764) teaches the one or more first TMVs ( Fig. 2B right side #540 ) and the one or more second TMVs ( Fig. 2B left side #540 ) each comprise a shape, within a plane perpendicular to a symmetry-axis, comprising a circle, a triangle, a square, or an n-sided polygon ( Fig. 1 #540 is circle ).
Claim 13: Kim (‘764), Song, and Shin disclose the semiconductor package of claim 3 ( as discussed above ).
Kim (‘764 ) teaches the one or more first TMVs ( Fig. 2B right side #540 ) and the one or more second TMVs ( Fig. 2B left side #540 ) each are arranged in a spatial configuration having at least one symmetry plane ( as shown in Fig. 2B ).
Claims 4-5, and 11 are rejected under U.S.C. 103 as being unpatentable over Kim; US 2020/0013764 A1; 01/2019 in view of Song et al.; US 2024/0088055 A1; 09/2023 and Shin et al.; US 2008/0073782 A1; 07/2007 as it relates to claim 3 above and further in view of Kulkarni; US 2021/0373240 A1; 05/2021
Claim 4: Kim (‘764) , Song, and Shin disclose the semiconductor package of claim 3 ( as described above ).
Neither Kim (‘764) nor Song nor Shin appear to disclose the first region comprises a diameter that is between 100 microns and 1000 microns; and the second region comprises an annular geometry having an inner diameter that is between 120 microns and 1600 microns and an outer diameter that is between 270 microns and 2000 microns.
However, Kulkarni teaches the first region ( Fig. 2 output tube 220 ) comprises a diameter that is between 100 microns and 1000 microns ( [0032] a diameter of 375 microns, and an outer diameter configured to be inserted into an alignment tube ); and the second region comprises an annular geometry having an inner diameter that is between 120 microns and 1600 microns ( [0033] The alignment tube 250 may include, for example, a tube, a sleeve, or the like having an inner diameter configured to accept a diameter of the input fiber 120, for example, a diameter of 500 microns ) and an outer diameter that is between 270 microns and 2000 microns ( outer diameter of Fig. 2 alignment tube 250 would be greater than 500 microns so it would satisfy this range ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kulkarni with Kim (‘764) and Song to implement the first region comprises a diameter that is between 100 microns and 1000 microns; and the second region comprises an annular geometry having an inner diameter that is between 120 microns and 1600 microns and an outer diameter that is between 270 microns and 2000 microns because these ranges balance electrical performance, manufacturability, and mechanical reliability.
Claim 5: Kim (‘764), Song, Shin, and Kulkarni disclose the semiconductor package of claim 4 ( as discussed above ).
Neither Kim (‘764) nor Song nor Shin appear to disclose the first region and the second region are separated from one another by a third region that comprises a further annular geometry having a width is between 10 microns and 300 microns.
However, Kulkarni teaches the first region ( Fig. 2 #220 ) and the second region ( Fig. 2 #250 ) are separated from one another by a third region ( Fig. 2 sizing tube 225 ) that comprises a further annular geometry having a width is between 10 microns and 300 microns ( [0032] the sizing tube 225 may have an inner diameter configured to accept the output tube 220 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kulkarni with Kim (‘764), Song, and Shin to implement the first region and the second region are separated from one another by a third region that comprises a further annular geometry having a width is between 10 microns and 300 microns because this approach allows for integration with other structures.
Claim 11: Kim (‘764), Song, and Shin disclose the semiconductor package of claim 9 ( as discussed above ).
Neither Kim (‘764) nor Song nor Shin appear to disclose the one or more second TMVs comprises a core-shell geometry; and the second specific dimension is between 50 microns and 1000 microns.
However, Kulkarni teaches the one or more second TMVs comprises a core-shell geometry ( Fig. 2 #250 ); and the second specific dimension is between 50 microns and 1000 microns ( [0033] The alignment tube 250 may include, for example, a tube, a sleeve, or the like having an inner diameter configured to accept a diameter of the input fiber 120, for example, a diameter of 500 microns ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kulkarni with Kim (‘764), Song, and Shin to implement the one or more second TMVs comprises a core-shell geometry; and the second specific dimension is between 50 microns and 1000 microns because this approach provides a design window that aligns with mold compound properties, electrical resistance trade-offs, and packaging density requirements.
Claims 6-7 are rejected under U.S.C. 103 as being unpatentable over Kim; US 2020/0013764 A1; 01/2019 in view of Song et al.; US 2024/0088055 A1; 09/2023, Shin et al.; US 2008/0073782 A1; 07/2007, and Kulkarni; US 2021/0373240 A1; 05/2021 as it relates to claim 4 above and further in view of Kim et al.; US 2021/0050297 A1; 04/2020
Claim 6: Kim (‘764), Song, Shin, and Kulkarni disclose the semiconductor package of claim 4 ( as discussed above ).
Neither Kim (‘764) nor Song nor Shin nor Kulkarni appear to disclose the one or more first TMVs located in the first region comprise a first pattern density that is between 0.5% and 5%; and the one or more second TMVs located in the second region comprise a second pattern density that is between 10% to 100%.
However, Kim ( ‘297 ) teaches the one or more first TMVs located in the first region comprise a first pattern density that is between 0.5% and 5% ( Fig. 2 150a ); and the one or more second TMVs located in the second region comprise a second pattern density that is between 10% to 100% ( Fig. 2 150b ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim (‘297 ) with Kim (‘764), Song, Shin, and Kulkarni to implement the one or more first TMVs located in the first region comprise a first pattern density that is between 0.5% and 5%; and the one or more second TMVs located in the second region comprise a second pattern density that is between 10% to 100% because these ranges are engineered to control depositition/etch uniformity and reliability.
Claim 7: Kim (‘764), Song, Shin, Kulkarni, and Kim ( ’297 ) disclose the semiconductor package of claim 6 ( as discussed above ).
Neither Kim (‘764) nor Song nor Shin nor Kulkarni appear to disclose a ratio of the second pattern density to the first pattern density is between 20 and 200.
However, Kim ( ‘297 ) teaches a ratio of the second pattern density to the first pattern density is between 20 and 200 ( Fig. 2 ratio of 150a to 150b ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim (‘297 ) with Kim (‘764), Song, Shin, and Kulkarni to implement a ratio of the second pattern density to the first pattern density is between 20 and 200 because this ratio balances between electrical performance, mechanical reliability, and yield and cost.
Claim 8 is rejected under U.S.C. 103 as being unpatentable over Kim; US 2020/0013764 A1; 01/2019 in view of Song et al.; US 2024/0088055 A1; 09/2023 and Shin et al.; US 2008/0073782 A1; 07/2007 as it relates to claim 3 above and further in view of Shigetoshi; US 2024/0145445 A1; 03/2022
Claim 8: Kim (‘764), Song, and Shin disclose the semiconductor package of claim 3 ( as discussed above ).
Neither Kim (‘764 ) nor Song nor Shin appear to disclose the one or more second TMVs comprises a single TMV having an annular geometry.
However, Shigetoshi teaches the one or more second TMVs comprises a single TMV having an annular geometry ( Fig. 2 through mold via 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Shigetoshi with Kim (‘764), Song, and Shin to implement the one or more second TMVs comprises a single TMV having an annular geometry because this approach is beneficial for electrical, mechanical, and process advantages.
Claim 12 is rejected under U.S.C. 103 as being unpatentable over Kim; US 2020/0013764 A1; 01/2019 in view of Song et al.; US 2024/0088055 A1; 09/2023 and Shin et al.; US 2008/0073782 A1; 07/2007 as it relates to claim 3 above and further in view of Ganesan et al.; US 2021/0305162 A1; 03/2020
Claim 12: Kim (‘764) and Song disclose the semiconductor package of claim 3 ( as discussed above ).
Neither Kim (‘764) nor Song appear to disclose the one or more first TMVs each comprise a shape, within a plane perpendicular to a symmetry axis, comprising two or more connected rectangular segments; and the first specific dimension is between 10 microns and 150 microns.
However, Ganesan teaches the one or more first TMVs each comprise a shape, within a plane perpendicular to a symmetry axis, comprising two or more connected rectangular segments ( [0025] the TMVs 163, 165 may have a circular, rectangular, or other shaped cross-section ); and the first specific dimension is between 10 microns and 150 microns ( [0025] an individual first TMV 163 may have a cross-section between 30 and 70 microns ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ganesan with Kim (‘764), Song, and Shin to implement the one or more first TMVs each comprise a shape, within a plane perpendicular to a symmetry axis, comprising two or more connected rectangular segments; and the first specific dimension is between 10 microns and 150 microns because this is a purpose built geometry to maximize electrical performance, mechanical reliability, and manufacturability.
Claim 18 is rejected under U.S.C. 103 as being unpatentable over Kim; US 2020/0013764 A1; 01/2019 in view of Song et al.; US 2024/0088055 A1; 09/2023 as it relates to claim 17 above and further in view of Park et al.; US 2024/0332150 A1; 01/2024
Claim 18: Kim (‘764) and Song disclose the method of claim 17 ( as discussed above ).
Neither Kim (‘764) nor Song appear to disclose forming the plurality of conductive vias further comprises: forming a patterned photoresist, comprising a plurality of via openings, over the substrate; and performing an electroplating process to deposit a conductive material in the via openings to thereby form the plurality of conductive vias, wherein forming the patterned photoresist further comprises forming the via openings such that the second specific dimension is between 100 microns and 500 microns and the first specific dimension is between 10 microns and 150 microns.
However, Park teaches forming the plurality of conductive vias further comprises: forming a patterned photoresist, comprising a plurality of via openings ( [0082] For example, a photoresist layer may be formed on the second surface 101b of the first redistribution wiring layer 100, and an exposure process may be performed on the photoresist layer to form a photoresist pattern having openings for forming the plurality of conductive vias on the second surface 101b of the second region R2 of the first redistribution wiring layer 100 ), over the substrate( Fig. 4 substrate C ) ; and performing an electroplating process to deposit a conductive material in the via openings to thereby form the plurality of conductive vias ( [0083] Then, an electroplating process may be performed to fill the openings of the photoresist pattern with a conductive material, to form the conductive vias 300. Then, the photoresist pattern may be removed by a strip process ), wherein forming the patterned photoresist further comprises forming the via openings such that the second specific dimension is between 100 microns and 500 microns and the first specific dimension is between 10 microns and 150 microns ( [0084] a diameter D1 of the conductive via 300 may be in a range of 30 μm to 100 μm, and a height H1 of the conductive via 300 may be in a range of 200 μm to 300 μm; second specific dimension is H1 and first is D1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Park with Kim (‘764) and Song to implement forming the plurality of conductive vias further comprises: forming a patterned photoresist, comprising a plurality of via openings, over the substrate; and performing an electroplating process to deposit a conductive material in the via openings to thereby form the plurality of conductive vias, wherein forming the patterned photoresist further comprises forming the via openings such that the second specific dimension is between 100 microns and 500 microns and the first specific dimension is between 10 microns and 150 microns because this approach is used to match photolithography resolution requirements and provide mechanical/chemical robustness in the fabrication steps.
Claim 20 is rejected under U.S.C. 103 as being unpatentable over Kim; US 2020/0013764 A1; 01/2019 in view of Song et al.; US 2024/0088055 A1; 09/2023 as it relates to claim 17 above and further in view of West et al.; US 2023/0282595 A1; 06/2022
Claim 20: Kim (‘764) and Song disclose the method of claim 17 ( as discussed above ).
Neither Kim (‘764) nor Song appear to disclose forming the plurality of conductive vias further comprises: forming the plurality of conductive vias to be configured as a plurality of repeat units separated by scribe lines, wherein each of the plurality of repeat units comprises one or more rectangular arrangements of conductive vias that are each located around a perimeter of a respective rectangular area to thereby form a plurality of rectangular areas; forming one or more first alignment marks comprising the first conductive via and the second conductive via within each of the plurality of repeat units; and forming one or more second alignment marks comprising the first conductive via and the second conductive via within one or more scribe lines between respective adjacent repeat units.
West discloses forming the plurality of conductive vias further comprises: forming the plurality of conductive vias ( [0043] In some arrangements, scribe seal 820 may include a plurality of conductor layers and conductive vias extending through one or more insulator layers disposed between the conductor layers ) to be configured as a plurality of repeat units separated by scribe lines ( Fig. 8A scribelanes 897 horizontal ), wherein each of the plurality of repeat units comprises one or more rectangular arrangements of conductive vias that are each located around a perimeter of a respective rectangular area to thereby form a plurality of rectangular areas ( as shown in Fig. 8A ); forming one or more first alignment marks comprising the first conductive via and the second conductive via within each of the plurality of repeat units ( [0020] it should be appreciated that the teachings herein may be equally applied, mutatis mutandis, to other scribelane structures such as, e.g., photo alignment marks ); and forming one or more second alignment marks ( Fig. 8A #897 vertical ) comprising the first conductive via and the second conductive via within one or more scribe lines between respective adjacent repeat units ( as shown in Fig. 8A ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of West with Kim (‘764) and Song to implement forming the plurality of conductive vias further comprises: forming the plurality of conductive vias to be configured as a plurality of repeat units separated by scribe lines, wherein each of the plurality of repeat units comprises one or more rectangular arrangements of conductive vias that are each located around a perimeter of a respective rectangular area to thereby form a plurality of rectangular areas; forming one or more first alignment marks comprising the first conductive via and the second conductive via within each of the plurality of repeat units; and forming one or more second alignment marks comprising the first conductive via and the second conductive via within one or more scribe lines between respective adjacent repeat units because the combination of scribe lines and alignment marks enables precise positioning of the wafer during fabrication and dicing.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.N.F./Examiner, Art Unit 2817
/BRADLEY SMITH/Primary Examiner, Art Unit 2817
Prosecution Insights