DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 8 is objected to because of the following informalities:
In line 3: “the least two trenches” should read --the at least two trenches--.
Claim 18 is objected to because of the following informalities:
In lines 2-3: “the least two trenches” should read --the at least two trenches--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, the claim recites “a number of the trenches is at least two” in lines 1-2, which is indefinite because it is unclear how the trench can be multiple elements when it is recited as a single element in claim 1.
For the purposes of examination, the trench recited in claim 1 will be interpreted as multiple elements.
Regarding claim 18, the claim recites “a number of the trenches is at least two” in lines 1-2, which is indefinite because it is unclear how the trench can be multiple elements when it is recited as a single element in claim 11.
For the purposes of examination, the trench recited in claim 11 will be interpreted as multiple elements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6, 8-9, 11-12, 14, 16, 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US 20210343881 A1) herein after “Cheng”.
Regarding claim 1, Fig. 6B of Cheng discloses a semiconductor device (Fig. 6B, IC 600b, ¶ [0035]), comprising:
a trench (Fig. 6B, trenches 102t, ¶ [0015]) formed in a substrate (Fig. 6B, semiconductor substrate 102, ¶ [0015]);
a capacitor structure (Fig. 6B, trench capacitor 106, ¶ [0015]) disposed in the trench (102t), the capacitor structure (106) comprising:
a bottom electrode layer (Fig. 6B, capacitor electrode layer 110c, ¶ [0017]) disposed in the trench (102t) and on a top surface of the substrate (102);
an insulating layer (Fig. 6B, capacitor dielectric layer 112c, ¶ [0017]) disposed on the bottom electrode layer (110c); and
a top electrode layer (Fig. 6B, capacitor electrode layer 110d, ¶ [0017]) disposed on the insulating layer (112c); and
a dielectric layer (Fig. 6B, capping dielectric layer 114, ¶ [0024]) disposed on the top electrode layer (110d), wherein a portion of the dielectric layer (114) is filled in the trench (102t), and the dielectric layer (114) comprises a recessed portion (shown in Fig. 6B) disposed above the trench (102t).
Regarding claim 2, Fig. 6B of Cheng discloses the semiconductor device of claim 1 as applied above, and Fig. 6B of Cheng further discloses wherein the recessed portion has a V-shaped cross section (shown in Fig. 6B).
Regarding claim 4, Fig. 6B of Cheng discloses the semiconductor device of claim 1 as applied above, and Fig. 6B of Cheng further discloses wherein the capacitor structure (106) comprises a first portion disposed in the trench (102t) and a second portion disposed on the top surface (Fig. 6B, front-side surface 102f, ¶ [0015]) of the substrate (102), and a bottom of the recessed portion is lower than a bottom of the second portion of the capacitor structure (106).
Regarding claim 6, Fig. 6B of Cheng discloses the semiconductor device of claim 1 as applied above, and Fig. 6B of Cheng further discloses wherein the dielectric layer (114) is formed with a void (Fig. 6B, cavity 103, ¶ [0018]), and the void (103) is located in the trench (102t).
Regarding claim 8, Fig. 6B of Cheng discloses the semiconductor device of claim 1 as applied above, and Fig. 6B of Cheng further discloses wherein a number of the trenches (102t) is at least two, and the capacitor structure (106) is disposed in the least two trenches (102t).
Regarding claim 9, Fig. 6B of Cheng discloses the semiconductor device of claim 1 as applied above, and Fig. 6B of Cheng further discloses wherein the dielectric layer (114) partially covers the capacitor structure (106), and the semiconductor device further comprises:
a protective layer (Fig. 6B, interconnect dielectric structure 122, ¶ [0030]) disposed on the dielectric layer (114) and a portion of the capacitor structure (106) not covered by the dielectric layer (114).
Regarding claim 11, Figs. 7-11 of Cheng disclose a method (“a method of forming an integrated circuit (IC) with a trench capacitor”, ¶ [0037]) for fabricating a semiconductor device (600b), comprising:
forming a trench (102t) in a substrate (Fig. 7, “a semiconductor substrate 102 is provided and is subsequently patterned to define at least a portion of trenches 102t”, ¶ [0038]);
forming a capacitor structure (106) in the trench (Fig. 11, “the capacitor electrode layers 110a-d and/or capacitor dielectric layers 112a-d are patterned, thereby defining a trench capacitor 106”, ¶ [0048]), comprising:
forming a bottom electrode layer (110c) in the trench (102t) and on a top surface of the substrate (102);
forming an insulating layer (112c) on the bottom electrode layer (110c); and
forming a top electrode layer (110d) on the insulating layer (112c); and
forming a dielectric layer (114) on the top electrode layer (“the capping dielectric layer 114 is formed such that it extends within each trench 102t”, ¶ [0047]), wherein a portion of the dielectric layer (114) is filled in the trench (102t), and the dielectric layer (114) comprises a recessed portion disposed above the trench (102t).
Regarding claim 12, Figs. 7-11 of Cheng disclose the method of claim 11 as applied above, and Fig. 6B of Cheng further discloses wherein the recessed portion has a V-shaped cross section (shown in Fig. 6B).
Regarding claim 14, Figs. 7-11 of Cheng disclose the method of claim 11 as applied above, and Fig. 6B of Cheng further discloses wherein the capacitor structure (106) comprises a first portion disposed in the trench (102t) and a second portion disposed on the top surface of the substrate (102), and a bottom of the recessed portion is lower than a bottom of the second portion of the capacitor structure (106).
Regarding claim 16, Figs. 7-11 of Cheng disclose the method of claim 11 as applied above, and Fig. 6B of Cheng further discloses wherein forming the dielectric layer (114) on the top electrode layer (110d) comprises forming a void (103) in the dielectric layer (114), and the void (103) is located in the trench (102t).
Regarding claim 18, Figs. 7-11 of Cheng disclose the method of claim 11 as applied above, and Fig. 6B of Cheng further discloses wherein a number of the trenches (102t) is at least two, and the capacitor structure (106) is disposed in the least two trenches (102t).
Regarding claim 19, Figs. 7-11 of Cheng disclose the method of claim 11 as applied above, and Figs. 10-12 of Cheng further discloses comprising:
removing a portion of the dielectric layer (114) located outside the trench (102t) to expose a portion of the capacitor structure (shown in Figs. 10-11), and
forming a protective layer (122) on the dielectric layer (114) and the portion of the capacitor structure (Fig. 12, “an inter-level dielectric (ILD) layer 406 is formed”, ¶ [0049]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 20210343881 A1).
Regarding claim 3, Fig. 6B of Cheng discloses the semiconductor device of claim 1 as applied above, and Fig. 6B of Cheng further discloses wherein the recessed portion has a width and a depth (shown in Fig. 6B), but fails to explicitly disclose that a ratio of the width to the depth is 1.5 to 1.9.
However, it would have been obvious to one of ordinary skill in the art to arrive at the claimed ratio through optimization of the trench dimensions and dielectric layer thickness and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Regarding claim 13, Figs. 7-11 of Cheng disclose the method of claim 11 as applied above, and Fig. 6B of Cheng further discloses wherein the recessed portion has a width and a depth (shown in Fig. 6B), but fails to explicitly disclose that a ratio of the width to the depth is 1.5 to 1.9.
However, it would have been obvious to one of ordinary skill in the art to arrive at the claimed ratio through optimization of the trench dimensions and dielectric layer thickness and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Claims 5, 7, 10, 15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 20210343881 A1) in view of Masuda et al. (US 20200005999 A1) herein after “Masuda”.
Regarding claim 5, Fig. 6B of Cheng discloses the semiconductor device of claim 1 as applied above, but Cheng fails to disclose wherein a thickness of the dielectric layer ranges from 200 angstroms to 500 angstroms.
In the similar field of endeavor of trench capacitors, Fig. 4 of Masuda discloses wherein a thickness of the dielectric layer (Fig. 4, barrier layer 30, ¶ [0044]) ranges from 120 angstroms to 500 angstroms (“The barrier layer 30 is formed to have a thickness of, for example, 5 nm to 500 nm. In one embodiment, the barrier layer 30 has a thickness of 50 nm”, ¶ [0073]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the dielectric layer of Cheng with the thickness as disclosed by Masuda, to protect the capacitor layers (see Masuda, ¶ [0073]) and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Regarding claim 7, Fig. 6B of Cheng discloses the semiconductor device of claim 1 as applied above, and Fig. 6B of Cheng further discloses wherein the trench (102t) has a depth and a width, but fails to explicitly disclose that a ratio of the depth to the width is 23 to 27.
In the similar field of endeavor of trench capacitors, Fig. 3 of Masuda discloses wherein the trench (Fig. 3, trenches 11, ¶ [0048]) has a depth and a width, and a ratio of the depth to the width is 23 to 27 (“Each of the plurality of trenches 11 has a width (a dimension in the X-axis direction) of, for example, 0.1 μm to 5 μm and a depth (a dimension in the Z-axis direction) of, for example, 1 μm to 100 μm”, ¶ ]0049]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the trenches of Cheng with the dimensions as disclosed by Masuda, to protect the capacitor layers (see Masuda, ¶ [0073]) and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Regarding claim 10, Fig. 6B of Cheng discloses the semiconductor device of claim 1 as applied above, but Cheng fails to disclose wherein a material of the protective layer comprises a nitride.
In the similar field of endeavor of trench capacitors, Fig. 4 of Masuda discloses wherein a material of the protective layer (40) comprises a nitride (“the protective layer 40 include… silicon nitride (SiN)”, ¶ [0074]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the protective layer of Cheng with the material as disclosed by Masuda, to protect the capacitor layers (see Masuda, ¶ [0074]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Regarding claim 15, Figs. 7-11 of Cheng discloses the method of claim 11 as applied above, but Cheng fails to disclose wherein a thickness of the dielectric layer ranges from 200 angstroms to 500 angstroms.
In the similar field of endeavor of trench capacitors, Fig. 4 of Masuda discloses wherein a thickness of the dielectric layer (30) ranges from 120 angstroms to 500 angstroms (“The barrier layer 30 is formed to have a thickness of, for example, 5 nm to 500 nm. In one embodiment, the barrier layer 30 has a thickness of 50 nm”, ¶ [0073]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the dielectric layer of Cheng with the thickness as disclosed by Masuda, to protect the capacitor layers (see Masuda, ¶ [0073]) and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Regarding claim 17, Figs. 7-11 of Cheng discloses the method of claim 11 as applied above, and Fig. 6B of Cheng further discloses wherein the trench (102t) has a depth and a width, but fails to explicitly disclose that a ratio of the depth to the width is 23 to 27.
In the similar field of endeavor of trench capacitors, Fig. 3 of Masuda discloses wherein the trench (Fig. 3, trenches 11, ¶ [0048]) has a depth and a width, and a ratio of the depth to the width is 23 to 27 (“Each of the plurality of trenches 11 has a width (a dimension in the X-axis direction) of, for example, 0.1 μm to 5 μm and a depth (a dimension in the Z-axis direction) of, for example, 1 μm to 100 μm”, ¶ ]0049]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the trenches of Cheng with the dimensions as disclosed by Masuda, to protect the capacitor layers (see Masuda, ¶ [0073]) and/or because changes in size and shape are prima facie obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)).
Regarding claim 20, Figs. 10-12 of Cheng discloses the method of claim 11 as applied above, but Cheng fails to disclose wherein a material of the protective layer comprises a nitride.
In the similar field of endeavor of trench capacitors, Fig. 4 of Masuda discloses wherein a material of the protective layer (40) comprises a nitride (“the protective layer 40 include… silicon nitride (SiN)”, ¶ [0074]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the protective layer of Cheng with the material as disclosed by Masuda, to protect the capacitor layers (see Masuda, ¶ [0074]) and/or because the use of conventional materials to perform their known function is prima-facie obvious (MPEP 2144.07).
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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